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Subject: Re: [PATCH v9 1/7] RISC-V: Clear SIP bit only when using SBI IPI
 operations
From:   Jessica Clarke <jrtc27@jrtc27.com>
In-Reply-To: <20220903161309.32848-2-apatel@ventanamicro.com>
Date:   Sat, 3 Sep 2022 21:16:14 +0100
Cc:     Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Atish Patra <atishp@atishpatra.org>,
        Alistair Francis <Alistair.Francis@wdc.com>,
        Anup Patel <anup@brainfault.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        linux-kernel@vger.kernel.org, Bin Meng <bmeng.cn@gmail.com>
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Message-Id: <6ABE254E-C7DA-468B-9A6B-D10FF32E0E89@jrtc27.com>
References: <20220903161309.32848-1-apatel@ventanamicro.com>
 <20220903161309.32848-2-apatel@ventanamicro.com>
To:     Anup Patel <apatel@ventanamicro.com>
Precedence: bulk

]On 3 Sept 2022, at 17:13, Anup Patel <apatel@ventanamicro.com> wrote:
>=20
> The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
> S-mode but read-only for M-mode so we clear this bit only when using
> SBI IPI operations.

Uh, where is this specified? I don=E2=80=99t see that, and that would be =
odd.
The spec clearly says that if supervisor software interrupts are
implemented then the bit is writeable, with no caveats on when (beyond
the permissions required to access the CSR in general).

This patch does make sense for a different reason though: that IPIs may
not be using software interrupts at all (in the IMSIC case).

Jess

> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> arch/riscv/kernel/sbi.c | 8 +++++++-
> arch/riscv/kernel/smp.c | 2 --
> 2 files changed, 7 insertions(+), 3 deletions(-)
>=20
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index 775d3322b422..fc614650a2e3 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -643,8 +643,14 @@ static void sbi_send_cpumask_ipi(const struct =
cpumask *target)
> 	sbi_send_ipi(target);
> }
>=20
> +static void sbi_ipi_clear(void)
> +{
> +	csr_clear(CSR_IP, IE_SIE);
> +}
> +
> static const struct riscv_ipi_ops sbi_ipi_ops =3D {
> -	.ipi_inject =3D sbi_send_cpumask_ipi
> +	.ipi_inject =3D sbi_send_cpumask_ipi,
> +	.ipi_clear =3D sbi_ipi_clear
> };
>=20
> void __init sbi_init(void)
> diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
> index 760a64518c58..c56d67f53ea9 100644
> --- a/arch/riscv/kernel/smp.c
> +++ b/arch/riscv/kernel/smp.c
> @@ -83,8 +83,6 @@ void riscv_clear_ipi(void)
> {
> 	if (ipi_ops && ipi_ops->ipi_clear)
> 		ipi_ops->ipi_clear();
> -
> -	csr_clear(CSR_IP, IE_SIE);
> }
> EXPORT_SYMBOL_GPL(riscv_clear_ipi);
>=20
> --=20
> 2.34.1
>=20
>=20
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