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Date:   Mon, 5 Sep 2022 10:07:04 +0300
From:   Mika Westerberg <mika.westerberg@linux.intel.com>
To:     Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc:     andreas.noever@gmail.com, michael.jamet@intel.com,
        YehezkelShB@gmail.com, sanju.mehta@amd.com,
        mario.limonciello@amd.com, linux-usb@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] thunderbolt: Resume PCIe bridges after switch is found
 on AMD USB4 controller
Message-ID: <YxWgGKIAvsxwSz85@black.fi.intel.com>
References: <20220905065622.1573811-1-kai.heng.feng@canonical.com>
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In-Reply-To: <20220905065622.1573811-1-kai.heng.feng@canonical.com>
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Hi,

On Mon, Sep 05, 2022 at 02:56:22PM +0800, Kai-Heng Feng wrote:
> AMD USB4 can not detect external PCIe devices like external NVMe when
> it's hotplugged, because card/link are not up:
> 
> pcieport 0000:00:04.1: pciehp: pciehp_check_link_active: lnk_status = 1101

I think the correct solution is then to block them from runtime
suspending entirely.

> Use `lspci` to resume pciehp bridges can find external devices.
> 
> A long delay before checking card/link presence doesn't help, either.
> The only way to make the hotplug work is to enable pciehp interrupt and
> check card presence after the TB switch is added.
> 
> Since the topology of USB4 and its PCIe bridges are siblings, hardcode
> the bridge ID so TBT driver can wake them up to check presence.

Let's not add PCI things into TBT driver unless absolutely necessary.

At least on Intel hardware the PCIe hotplug is signaled by SCI when the
root port is in D3, I wonder if AMD has something similar.