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From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
To:     matthias.bgg@gmail.com
Cc:     mturquette@baylibre.com, sboyd@kernel.org,
        angelogioacchino.delregno@collabora.com, wenst@chromium.org,
        miles.chen@mediatek.com, rex-bc.chen@mediatek.com,
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        krzysztof.kozlowski+dt@linaro.org
Subject: [PATCH 08/10] clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents
Date:   Mon,  5 Sep 2022 12:04:14 +0200
Message-Id: <20220905100416.42421-9-angelogioacchino.delregno@collabora.com>
In-Reply-To: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com>
References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com>
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These PLLs are conflicting with GPU rates that can be generated by
the GPU-dedicated MFGPLL and would require a special clock handler
to be used, for very little and ignorable power consumption benefits.
Also, we're in any case unable to set the rate of these PLLs to
something else that is sensible for this task, so simply drop them:
this will make the GPU to be clocked exclusively from MFGPLL for
"fast" rates, while still achieving the right "safe" rate during
PLL frequency locking.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8195-topckgen.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c
index 4dde23bece66..6ff610c101ae 100644
--- a/drivers/clk/mediatek/clk-mt8195-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c
@@ -301,8 +301,6 @@ static const char * const ipu_if_parents[] = {
 static const char * const mfg_parents[] = {
 	"clk26m",
 	"mainpll_d5_d2",
-	"univpll_d6",
-	"univpll_d7"
 };
 
 static const char * const camtg_parents[] = {
-- 
2.37.2