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Message-ID: <4e61b63b-74ac-1682-968f-17e5d8db7ce6@linaro.org>
Date:   Mon, 5 Sep 2022 15:09:07 +0200
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Subject: Re: [PATCH v4 1/2] dt-bindings: phy: ti: phy-gmii-sel: Add bindings
 for J7200
Content-Language: en-US
To:     Siddharth Vadapalli <s-vadapalli@ti.com>,
        krzysztof.kozlowski+dt@linaro.org
Cc:     robh+dt@kernel.org, lee.jones@linaro.org, kishon@ti.com,
        vkoul@kernel.org, dan.carpenter@oracle.com,
        grygorii.strashko@ti.com, rogerq@kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-phy@lists.infradead.org
References: <20220901085506.138633-1-s-vadapalli@ti.com>
 <20220901085506.138633-2-s-vadapalli@ti.com>
 <4b681c03-7f5a-0234-2276-316e0bad1de5@linaro.org>
 <44339382-c4e2-26db-de5d-263ae5a585b8@ti.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <44339382-c4e2-26db-de5d-263ae5a585b8@ti.com>
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Precedence: bulk

On 02/09/2022 08:09, Siddharth Vadapalli wrote:
> Hello Krzysztof,
> 
> On 01/09/22 20:51, Krzysztof Kozlowski wrote:
>> On 01/09/2022 11:55, Siddharth Vadapalli wrote:
>>> TI's J7200 SoC supports additional PHY modes like QSGMII and SGMII
>>> that are not supported on earlier SoCs. Add a compatible for it.
>>>
>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>> ---
>>>  .../mfd/ti,j721e-system-controller.yaml       |  6 ++++
>>>  .../bindings/phy/ti,phy-gmii-sel.yaml         | 30 ++++++++++++++++++-
>>>  2 files changed, 35 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>>> index 1aeac43cad92..802374e7645f 100644
>>> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>>> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>>> @@ -54,6 +54,12 @@ patternProperties:
>>>      description:
>>>        Clock provider for TI EHRPWM nodes.
>>>  
>>> +  "phy@[0-9a-f]+$":
>>> +    type: object
>>> +    $ref: /schemas/phy/phy-provider.yaml
>>
>> You need instead ref to specific device bindings/schema. Probably to
>> /schemas/phy/ti,phy-gmii-sel.yaml#
> 
> Thank you for the clarification. I will update $ref to
> "/schemas/phy/ti,phy-gmii-sel.yaml#" in the v5 series.
> 
>>
>> This was entirely different in v3, so your change is very confusing.
> 
> I had misunderstood Rob's comment in the v3 patch. I had initially
> provided the relative path to the bindings file ti,phy-gmii-sel.yaml in
> the v3 patch. When Rob commented "/schemas/phy/..", I misunderstood and
> thought that I had to point $ref to a generic phy-provider schema
> present in the dt-schema repo and thus, in this v4 patch, I had updated
> $ref accordingly.
> 
>>
>>> +    description:
>>> +      This is the register to set phy mode through phy-gmii-sel driver.
>>
>> I don't understand the description. Please focus on the hardware not
>> some drivers - what is here? Phy for something?
> 
> I will fix the description, updating it to the following:
> "Address of the CTRLMMR_ENETx_CTRL registers which are used to configure
> the phy-mode of the CPSW MAC ports."
> 
> Please let me know if the above description is fine.

Hm, but that's a phy node, not address of register... Isn't this a phy
node representing the phy of the CPSW MAC ports?

> 
>>
>>> +
>>>  required:
>>>    - compatible
>>>    - reg
>>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>>> index ff8a6d9eb153..0ffb97f1a77c 100644
>>> --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>>> @@ -53,12 +53,24 @@ properties:
>>>        - ti,am43xx-phy-gmii-sel
>>>        - ti,dm814-phy-gmii-sel
>>>        - ti,am654-phy-gmii-sel
>>> +      - ti,j7200-cpsw5g-phy-gmii-sel
>>>  
>>>    reg:
>>>      maxItems: 1
>>>  
>>>    '#phy-cells': true
>>>  
>>> +  ti,qsgmii-main-ports:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>>> +    description: |
>>> +      Required only for QSGMII mode. Array to select the port for
>>> +      QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
>>> +      ports automatically. Any one of the 4 CPSW5G ports can act as the
>>> +      main port with the rest of them being the QSGMII_SUB ports.
>>> +    items:
>>> +      minimum: 1
>>> +      maximum: 4
>>> +
>>>  allOf:
>>>    - if:
>>>        properties:
>>> @@ -73,6 +85,22 @@ allOf:
>>>          '#phy-cells':
>>>            const: 1
>>>            description: CPSW port number (starting from 1)
>>
>> Blank line
> 
> I will fix this in the v5 series.
> 
>>
>>
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - ti,j7200-cpsw5g-phy-gmii-sel
>>> +    then:
>>> +      properties:
>>> +        '#phy-cells':
>>> +          const: 1
>>> +          description: CPSW port number (starting from 1)
>>> +        ti,qsgmii-main-ports:
>>> +          maxItems: 1
>>
>> It does not really make sense to limit items here, in the context of
>> this patch. You got a comment for it already. Your patch should make
>> sense on its own.
> 
> I had defined the property as an array because there are more than one
> QSGMII main ports for other devices for which I will be posting the
> patches. I had planned to reuse this property, with "maxItems: 2" in the
> future patches for other compatibles. However, as suggested by you, I
> will change the property to a uint32 instead of uint32-array in this
> series. Later, in my future patches for other devices, I will change it
> back to a uint32-array when I reuse the property.

Wait, no. You should not change the property. This should be
uint32-array, because you will extend it soon, just maxItems must be
defined in top-level place.

Best regards,
Krzysztof