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Date:   Mon, 5 Sep 2022 16:18:29 +0300
From:   Mika Westerberg <mika.westerberg@linux.intel.com>
To:     Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc:     andreas.noever@gmail.com, michael.jamet@intel.com,
        YehezkelShB@gmail.com, sanju.mehta@amd.com,
        mario.limonciello@amd.com, linux-usb@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] thunderbolt: Resume PCIe bridges after switch is found
 on AMD USB4 controller
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 <YxWqSYDWe0NitSkL@black.fi.intel.com>
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Hi,

On Mon, Sep 05, 2022 at 10:50:33AM +0300, Mika Westerberg wrote:
> > Yes those root ports are resumed to D0 when something is plugged. They
> > however fail to detect any externel PCIe devices.
> 
> Hmm, so you see the actual hotplug but the tunneled PCIe link may not be
> detected? Does the PCIe "Card Present" (or Data Link Layer Active)
> status change at all or is it always 0?

I wonder if we are simply missing the required delays here? Looking at
the lspci dump in the bugzilla you refer the root port 03.1 supports
active link reporting:

		LnkCap:	Port #247, Speed 2.5GT/s, Width x1, ASPM L1, Exit Latency L1 <4us
			ClockPM- Surprise- LLActRep+ BwNot- ASPMOptComp+

So when the link goes back to L0 (D3 -> D0 transition) the kernel should
issue the 100+ ms reset delay in pci_bridge_wait_for_secondary_bus():

  https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/pci.c#n5045

can you check if that is happening? It should show up in the dmesg when
CONFIG_PCI_DEBUG=y but I don't see it in yours.