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References: <20220905123946.95223-1-likexu@tencent.com> <20220905123946.95223-5-likexu@tencent.com>
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From:   Jim Mattson <jmattson@google.com>
Date:   Mon, 5 Sep 2022 10:36:51 -0700
Message-ID: <CALMp9eQtjZ-iRiW5Jusa+NF-P0sdHtcoR8fPiBSKtNXKgstgVA@mail.gmail.com>
Subject: Re: [PATCH 4/4] KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022
To:     Like Xu <like.xu.linux@gmail.com>
Cc:     Sean Christopherson <seanjc@google.com>,
        Paolo Bonzini <pbonzini@redhat.com>,
        Sandipan Das <sandipan.das@amd.com>, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org
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On Mon, Sep 5, 2022 at 5:45 AM Like Xu <like.xu.linux@gmail.com> wrote:
>
> From: Sandipan Das <sandipan.das@amd.com>
>
> CPUID leaf 0x80000022 i.e. ExtPerfMonAndDbg advertises some
> new performance monitoring features for AMD processors.
>
> Bit 0 of EAX indicates support for Performance Monitoring
> Version 2 (PerfMonV2) features. If found to be set during
> PMU initialization, the EBX bits of the same CPUID function
> can be used to determine the number of available PMCs for
> different PMU types.
>
> Expose the relevant bits via KVM_GET_SUPPORTED_CPUID so
> that guests can make use of the PerfMonV2 features.
>
> Co-developed-by: Like Xu <likexu@tencent.com>
> Signed-off-by: Like Xu <likexu@tencent.com>
> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
> ---
>  arch/x86/include/asm/perf_event.h |  8 ++++++++
>  arch/x86/kvm/cpuid.c              | 21 ++++++++++++++++++++-
>  2 files changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index f6fc8dd51ef4..c848f504e467 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -214,6 +214,14 @@ union cpuid_0x80000022_ebx {
>         unsigned int            full;
>  };
>
> +union cpuid_0x80000022_eax {
> +       struct {
> +               /* Performance Monitoring Version 2 Supported */
> +               unsigned int    perfmon_v2:1;
> +       } split;
> +       unsigned int            full;
> +};
> +
>  struct x86_pmu_capability {
>         int             version;
>         int             num_counters_gp;
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 75dcf7a72605..08a29ab096d2 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -1094,7 +1094,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
>                 entry->edx = 0;
>                 break;
>         case 0x80000000:
> -               entry->eax = min(entry->eax, 0x80000021);
> +               entry->eax = min(entry->eax, 0x80000022);
>                 /*
>                  * Serializing LFENCE is reported in a multitude of ways, and
>                  * NullSegClearsBase is not reported in CPUID on Zen2; help
> @@ -1203,6 +1203,25 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
>                 if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
>                         entry->eax |= BIT(6);
>                 break;
> +       /* AMD Extended Performance Monitoring and Debug */
> +       case 0x80000022: {
> +               union cpuid_0x80000022_eax eax;
> +               union cpuid_0x80000022_ebx ebx;
> +
> +               entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
> +               if (!enable_pmu)
> +                       break;
> +
> +               if (kvm_pmu_cap.version > 1) {
> +                       /* AMD PerfMon is only supported up to V2 in the KVM. */
> +                       eax.split.perfmon_v2 = 1;
> +                       ebx.split.num_core_pmc = min(kvm_pmu_cap.num_counters_gp,
> +                                                    KVM_AMD_PMC_MAX_GENERIC);

Note that the number of core PMCs has to be at least 6 if
guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE). I suppose this leaf
could claim fewer, but the first 6 PMCs must work, per the v1 PMU
spec. That is, software that knows about PERFCTR_CORE, but not about
PMU v2, can rightfully expect 6 PMCs.


> +               }
> +               entry->eax = eax.full;
> +               entry->ebx = ebx.full;
> +               break;
> +       }
>         /*Add support for Centaur's CPUID instruction*/
>         case 0xC0000000:
>                 /*Just support up to 0xC0000004 now*/
> --
> 2.37.3
>