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From:   <Conor.Dooley@microchip.com>
To:     <zong.li@sifive.com>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>,
        <paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
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        <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
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Subject: Re: [PATCH v2 3/6] soc: sifive: ccache: determine the cache level
 from dts
Thread-Topic: [PATCH v2 3/6] soc: sifive: ccache: determine the cache level
 from dts
Thread-Index: AQHYwQH8Nup3uTCbTkOlLkhrlQaRlK3RJMGA
Date:   Mon, 5 Sep 2022 18:14:49 +0000
Message-ID: <cf98f606-a392-37e9-be92-cb854afb4951@microchip.com>
References: <20220905083125.29426-1-zong.li@sifive.com>
 <20220905083125.29426-4-zong.li@sifive.com>
In-Reply-To: <20220905083125.29426-4-zong.li@sifive.com>
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