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From:   Zong Li <zongbox@gmail.com>
Date:   Tue, 6 Sep 2022 09:57:40 +0800
Message-ID: <CA+ZOyaheXVbETyj6YFMn4sb25Feqm9AV0EuuKDbaRXJjAY+_tQ@mail.gmail.com>
Subject: Re: [PATCH v2 3/6] soc: sifive: ccache: determine the cache level
 from dts
To:     Conor.Dooley@microchip.com
Cc:     zong.li@sifive.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com,
        paul.walmsley@sifive.com, aou@eecs.berkeley.edu,
        greentime.hu@sifive.com, ben.dooks@sifive.com, bp@alien8.de,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
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<Conor.Dooley@microchip.com> =E6=96=BC 2022=E5=B9=B49=E6=9C=886=E6=97=A5 =
=E9=80=B1=E4=BA=8C =E5=87=8C=E6=99=A82:56=E5=AF=AB=E9=81=93=EF=BC=9A
>
> On 05/09/2022 09:31, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know =
the content is safe
> >
> > Composable cache could be L2 or L3 cache, use 'cache-level' property of
> > device node to determine the level.
> >
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> >  drivers/soc/sifive/sifive_ccache.c | 6 +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/si=
five_ccache.c
> > index 1b16a196547f..0e0eb85c94d8 100644
> > --- a/drivers/soc/sifive/sifive_ccache.c
> > +++ b/drivers/soc/sifive/sifive_ccache.c
> > @@ -38,6 +38,7 @@
> >  static void __iomem *ccache_base;
> >  static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
> >  static struct riscv_cacheinfo_ops ccache_cache_ops;
> > +static int level;
>
> Can you have a system with a composable l2 & l3 cache?

We don't have a system with composable L2 and L3 cache at same time.
But as I mentioned in the thread of second patch, we use another cache
as L2 when the composable cache used for L3.

>
> >
> >  enum {
> >         DIR_CORR =3D 0,
> > @@ -143,7 +144,7 @@ static const struct attribute_group priv_attr_group=
 =3D {
> >  static const struct attribute_group *ccache_get_priv_group(struct cach=
einfo *this_leaf)
> >  {
> >         /* We want to use private group for composable cache only */
> > -       if (this_leaf->level =3D=3D 2)
> > +       if (this_leaf->level =3D=3D level)
> >                 return &priv_attr_group;
> >         else
> >                 return NULL;
> > @@ -210,6 +211,9 @@ static int __init sifive_ccache_init(void)
> >         if (!ccache_base)
> >                 return -ENOMEM;
> >
> > +       if (of_property_read_u32(np, "cache-level", &level))
> > +               return -ENODEV;
> > +
> >         intr_num =3D of_property_count_u32_elems(np, "interrupts");
> >         if (!intr_num) {
> >                 pr_err("CCACHE: no interrupts property\n");
> > --
> > 2.17.1
> >
>