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From:   Conor Dooley <conor.dooley@microchip.com>
To:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Conor Dooley <conor.dooley@microchip.com>,
        "Daire McNamara" <daire.mcnamara@microchip.com>
CC:     <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
Subject: [PATCH v1 0/3] Add a devicetree for the Aldec PolarFire SoC TySoM
Date:   Tue, 6 Sep 2022 13:15:23 +0100
Message-ID: <20220906121525.3212705-1-conor.dooley@microchip.com>
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Hey All,

On top of my other series adding the m100pfsevp and sevkit [0], here's
yet another development kit.. This time from Aldec.

The board has 32 GB of DDR but the DT I have access to only has a small
bit of that mapped.. until I know exactly what the mapping is, I will
not be applying this.

Thanks,
Conor.

0 - https://lore.kernel.org/all/20220901133403.3392291-1-conor.dooley@microchip.com/

Conor Dooley (3):
  dt-bindings: vendor-prefixes: Add entry for Aldec
  dt-bindings: riscv: microchip: document the Aldec TySoM
  riscv: dts: microchip: add a devicetree for the Aldec TySoM

 .../devicetree/bindings/riscv/microchip.yaml  |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/riscv/boot/dts/microchip/Makefile        |   1 +
 .../dts/microchip/mpfs-tysom-m-fabric.dtsi    |  47 +++++
 .../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 168 ++++++++++++++++++
 5 files changed, 219 insertions(+)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts

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