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Date:   Wed, 7 Sep 2022 15:39:38 -0500
From:   Rob Herring <robh@kernel.org>
To:     Conor Dooley <conor.dooley@microchip.com>
Cc:     Lewis Hanly <lewis.hanly@microchip.com>,
        Daire McNamara <daire.mcnamara@microchip.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Vattipalli Praveen <praveen.kumar@microchip.com>,
        Rob Herring <robh+dt@kernel.org>,
        Hugh Breslin <hugh.breslin@microchip.com>,
        Shravan Chippa <shravan.chippa@microchip.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Wolfgang Grandegger <wg@aries-embedded.de>,
        devicetree@vger.kernel.org, Cyril Jean <Cyril.Jean@microchip.com>
Subject: Re: [PATCH v3 2/9] dt-bindings: riscv: microchip: document the aries
 m100pfsevp
Message-ID: <20220907203938.GA301364-robh@kernel.org>
References: <20220901133403.3392291-1-conor.dooley@microchip.com>
 <20220901133403.3392291-3-conor.dooley@microchip.com>
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On Thu, 01 Sep 2022 14:33:57 +0100, Conor Dooley wrote:
> Add a compatible for the Aries Embedded M100PFSEVP SOM + EVK platform.
> 
> Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>