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[2620:137:e000::1:20]) by mx.google.com with ESMTP id rm6-20020a17090b3ec600b001fb3040753fsi413702pjb.64.2022.09.07.15.22.05; Wed, 07 Sep 2022 15:22:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ByYw6y7Y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230397AbiIGVwE (ORCPT + 99 others); Wed, 7 Sep 2022 17:52:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230364AbiIGVv6 (ORCPT ); Wed, 7 Sep 2022 17:51:58 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 998CDBD15D for ; Wed, 7 Sep 2022 14:51:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662587517; x=1694123517; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BGxae1nA6Nr/6+rxbpBDV1g74jZ8OEr+jGn8KW/3em0=; b=ByYw6y7YKMOb+woxIsPWT/DiukzPoCv+spOW7B/lsTV9qQqsn1Pu0ijO qBbuIhPK0y0jhAHoQAhMSSALMBCLTQqpPYGN7gFq+ij/1O/bzzSQnniNI AeXYGuDwUdve/j3UGwdNOCrhgYWqxYuAEHR2P6uoUizFC/GdPqV8Ia54B E+XspznUlGX18HBfJA0N6JVAzmyDRiVommqTOR1AfQC0AfvmOzSdF8yZ8 lr181wElehO/pS5YahybUJU0XyZPUpgIZ9FtQoa4G60Q2ZwFcPGDMpQ87 O+YmAoraZdVhe1q08tfmDjBI/nRpPOUyYK4321M+vte1GWTi8GsBNxPqg g==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="295740287" X-IronPort-AV: E=Sophos;i="5.93,298,1654585200"; d="scan'208";a="295740287" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 14:51:50 -0700 X-IronPort-AV: E=Sophos;i="5.93,298,1654585200"; d="scan'208";a="790207877" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 14:51:46 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart , Daniele Ceraolo Spurio Subject: [PATCH v9 05/16] drm/i915/gsc: add GSC XeHP SDV platform definition Date: Thu, 8 Sep 2022 00:51:02 +0300 Message-Id: <20220907215113.1596567-6-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907215113.1596567-1-tomas.winkler@intel.com> References: <20220907215113.1596567-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexander Usyskin Define GSC on XeHP SDV (Intel(R) dGPU without display) XeHP SDV uses the same hardware settings as DG1, but uses polling instead of interrupts and runs the firmware in slow pace due to hardware limitations. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Reviewed-by: Daniele Ceraolo Spurio --- V9: Rebase drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c index 73498c2574c8..e1040c8f2fd3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = { } }; +static const struct gsc_def gsc_def_xehpsdv[] = { + { + /* HECI1 not enabled on the device. */ + }, + { + .name = "mei-gscfi", + .bar = DG1_GSC_HECI2_BASE, + .bar_size = GSC_BAR_LENGTH, + .use_polling = true, + .slow_firmware = true, + } +}; + static const struct gsc_def gsc_def_dg2[] = { { .name = "mei-gsc", @@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915, if (IS_DG1(i915)) { def = &gsc_def_dg1[intf_id]; + } else if (IS_XEHPSDV(i915)) { + def = &gsc_def_xehpsdv[intf_id]; } else if (IS_DG2(i915)) { def = &gsc_def_dg2[intf_id]; } else { -- 2.37.2