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Date:   Wed, 7 Sep 2022 16:26:49 -0500
From:   Bjorn Helgaas <helgaas@kernel.org>
To:     William McVicker <willmcvicker@google.com>
Cc:     Bjorn Helgaas <bhelgaas@google.com>, kernel-team@android.com,
        Sajid Dalvi <sdalvi@google.com>,
        Matthias Kaehlcke <mka@chromium.org>,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3] PCI/PM: Switch D3Hot delay to also use usleep_range
Message-ID: <20220907212649.GA152425@bhelgaas>
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On Wed, Sep 07, 2022 at 12:07:03AM +0000, William McVicker wrote:
> On 09/02/2022, Bjorn Helgaas wrote:

> >    static void pci_dev_d3_sleep(struct pci_dev *dev)
> >    {
> >         unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
> >         unsigned int upper;
> > 
> >         if (delay_ms) {
> >                 /* 20% upper bound, 1ms minimum */
> >                 upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U)
> >                 usleep_range(delay_ms * USEC_PER_MSEC,
> >                              (delay_ms + upper) * USEC_PER_MSEC);
> >         }
> >    }
> > 
> > Since the Intel quirk is for 120ms, a 20% upper bound would make the
> > range 120-144ms.  Would that be a problem?  Those chips are ancient;
> > the list is untouched since it was added in 2006.  The point of
> > usleep_range() is to allow the scheduler to coalesce the wakeup with
> > other events, so it seems unlikely we'd ever wait the whole 144ms.  I
> > vote for optimizing the readability over sleep/resume time for
> > already-broken chips.
> 
> I'm totally fine with this, but I don't really know what the impact
> would be to those old Intel chips.

Worst-case, a few more ms to wakeup.  Since we're starting with a huge
120ms *per device* delay, I think that's acceptable.  Let's do this.

Bjorn