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From:   Miles Chen <miles.chen@mediatek.com>
To:     <angelogioacchino.delregno@collabora.com>
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Subject: Re: [PATCH 03/10] clk: mediatek: mux: add clk notifier functions
Date:   Thu, 8 Sep 2022 06:59:57 +0800
Message-ID: <20220907225957.10541-1-miles.chen@mediatek.com>
In-Reply-To: <20220905100416.42421-4-angelogioacchino.delregno@collabora.com>
References: <20220905100416.42421-4-angelogioacchino.delregno@collabora.com>
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> From: Chen-Yu Tsai <wenst@chromium.org>
> 
> With device frequency scaling, the mux clock that (indirectly) feeds the
> device selects between a dedicated PLL, and some other stable clocks.
> 
> When a clk rate change is requested, the (normally) upstream PLL is
> reconfigured. It's possible for the clock output of the PLL to become
> unstable during this process.
> 
> To avoid causing the device to glitch, the mux should temporarily be
> switched over to another "stable" clock during the PLL rate change.
> This is done with clk notifiers.
> 
> This patch adds common functions for notifiers to temporarily and
> transparently reparent mux clocks.
> 
> This was loosely based on commit 8adfb08605a9 ("clk: sunxi-ng: mux: Add
> clk notifier functions").
>

Reviewed-by: Miles Chen <miles.chen@mediatek.com>