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From:   Miles Chen <miles.chen@mediatek.com>
To:     <angelogioacchino.delregno@collabora.com>
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Subject: Re: [PATCH 04/10] clk: mediatek: mt8183: Add clk mux notifier for MFG mux
Date:   Thu, 8 Sep 2022 07:04:42 +0800
Message-ID: <20220907230442.10633-1-miles.chen@mediatek.com>
In-Reply-To: <20220905100416.42421-5-angelogioacchino.delregno@collabora.com>
References: <20220905100416.42421-5-angelogioacchino.delregno@collabora.com>
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> When the MFG PLL clock, which is upstream of the MFG clock, is changed,
> the downstream clock and consumers need to be switched away from the PLL
> over to a stable clock to avoid glitches.
> 
> This is done through the use of the newly added clk mux notifier. The
> notifier is set on the mux itself instead of the upstream PLL, but in
> practice this works, as the rate change notifitcations are propogated
> throughout the sub-tree hanging off the PLL. Just before rate changes,
> the MFG mux is temporarily and transparently switched to the 26 MHz
> main crystal. After the rate change, the mux is switched back.
> 
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> [Angelo: Rebased to assign clk_ops in mtk_mux_nb]
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Miles Chen <miles.chen@mediatek.com>