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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id b4-20020a170902d40400b001750361f430sm4484728ple.155.2022.09.08.07.44.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 07:44:29 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v3 0/6] Use composable cache instead of L2 cache Date: Thu, 8 Sep 2022 14:44:18 +0000 Message-Id: <20220908144424.4232-1-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since composable cache may be L3 cache if private L2 cache exists, we should use its original name "composable cache" to prevent confusion. This patchset contains the modification which is related to ccache, such as DT binding and EDAC driver. The DT binding is based on top of Conor's patch, it has got ready for merging, and it looks that it would be taken into the next few 6.0-rc version. If there is any change, the next version of this series will be posted as well. https://lore.kernel.org/linux-riscv/20220825180417.1259360-2-mail@conchuod.ie/ Ben Dooks (2): soc: sifive: ccache: reduce printing on init soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Zong Li (4): dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache soc: sifive: ccache: rename SiFive L2 cache to Composable cache. soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: define the macro for the register shifts ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 ++- drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 12 +- drivers/soc/sifive/Kconfig | 6 +- drivers/soc/sifive/Makefile | 2 +- .../{sifive_l2_cache.c => sifive_ccache.c} | 200 ++++++++++-------- .../{sifive_l2_cache.h => sifive_ccache.h} | 16 +- 7 files changed, 151 insertions(+), 115 deletions(-) rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%) rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (31%) rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%) -- 2.17.1