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Date:   Thu, 8 Sep 2022 14:42:58 -0500
From:   Rob Herring <robh@kernel.org>
To:     Richard Zhu <hongxing.zhu@nxp.com>
Cc:     l.stach@pengutronix.de, richard.leitner@linux.dev,
        vkoul@kernel.org, shawnguo@kernel.org, bhelgaas@google.com,
        alexander.stein@ew.tq-group.com, linux-phy@lists.infradead.org,
        kernel@pengutronix.de, devicetree@vger.kernel.org,
        linux-imx@nxp.com, p.zabel@pengutronix.de,
        lorenzo.pieralisi@arm.com, marex@denx.de,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 1/7] dt-binding: phy: Add iMX8MP PCIe PHY binding
Message-ID: <20220908194258.GA3217149-robh@kernel.org>
References: <1662109086-15881-1-git-send-email-hongxing.zhu@nxp.com>
 <1662109086-15881-2-git-send-email-hongxing.zhu@nxp.com>
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On Fri, 02 Sep 2022 16:58:00 +0800, Richard Zhu wrote:
> Add i.MX8MP PCIe PHY binding.
> On iMX8MM, the initialized default value of PERST bit(BIT3) of
> SRC_PCIEPHY_RCR is 1b'1.
> But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> 
> And the PERST bit should be kept 1b'1 after power and clocks are stable.
> So add one more PERST explicitly for i.MX8MP PCIe PHY.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../bindings/phy/fsl,imx8-pcie-phy.yaml          | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>