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[2620:137:e000::1:20]) by mx.google.com with ESMTP id w71-20020a63824a000000b0042b5909feb4si411339pgd.727.2022.09.09.05.32.58; Fri, 09 Sep 2022 05:33:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=D2xNU3+4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231290AbiIIMYg (ORCPT + 99 others); Fri, 9 Sep 2022 08:24:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231331AbiIIMYH (ORCPT ); Fri, 9 Sep 2022 08:24:07 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 787A1267 for ; Fri, 9 Sep 2022 05:23:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 2A3D1B82348 for ; Fri, 9 Sep 2022 12:23:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C9AC6C433D7; Fri, 9 Sep 2022 12:23:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662726220; bh=Imk5yUk/jOLKNZON/UMwhEo4N9r1Vnq0lW69XsiyL7E=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=D2xNU3+4KqtlHTplYxRJ64OBbanZp2rjzf1R3McRrmqLE1/tgUnibsEZaz/AzSchT Qqg/BuBiqvLlIOLx+tc+ysjfEzymphRrvjfD/TGOsUKDH/p9h7b+lDQtmz2HiQeMM5 ITIbW1msSMe1pjVb/fUAY47KIZ/a4H0zBXWhuVDuGKy0f/nVKfNJttbZAQpd3q1pAq SAKTOMzERYGeStO7yg5Asbe7iUcmgHPpCoMQJIyWJzxIPg6uIWRkWiok6e9Ol1T3Ru KQ38i4Q/R0iRWydZJL6+kp73FkSGS1j+z4gBMvWSPBkKojSl+LaWhAzmkOUckOZznp qhlJvOK11hAGQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oWd2o-009BDK-Qh; Fri, 09 Sep 2022 13:23:38 +0100 Date: Fri, 09 Sep 2022 13:23:38 +0100 Message-ID: <87czc4rb1x.wl-maz@kernel.org> From: Marc Zyngier To: Kunkun Jiang Cc: Mark Rutland , "Daniel Lezcano" , Thomas Gleixner , "wanghaibin.wang@huawei.com" , Zenghui Yu , , Subject: Re: A question about Cortex-A73 erratum 858921 In-Reply-To: References: User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: jiangkunkun@huawei.com, mark.rutland@arm.com, daniel.lezcano@linaro.org, tglx@linutronix.de, wanghaibin.wang@huawei.com, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 09 Sep 2022 08:31:43 +0100, Kunkun Jiang wrote: > > Hi all, > > Recently I am learning the code related to Arm arch timer. I found that the > Cortex-A73 erratum 858921 does not set the corresponding callback functions: > set_next_event_phys and set_next_event_virt like other erratums. Won't it > get the wrong value when reading the counter during setting next event? Yup, you're correct. This is a regression introduced by a38b71b0833e ("clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL"). We used to use the TVAL accessor which doesn't need a read of the counter, while the switch to CVAL needs one. Obviously, I didn't enough pay attention to the A73 erratum. Please send in a fix for this. Thanks, M. -- Without deviation from the norm, progress is not possible.