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Date:   Fri, 9 Sep 2022 15:57:45 +0300
From:   Serge Semin <fancer.lancer@gmail.com>
To:     Rob Herring <robh@kernel.org>
Cc:     Serge Semin <Sergey.Semin@baikalelectronics.ru>,
        Michal Simek <michal.simek@xilinx.com>,
        Borislav Petkov <bp@alien8.de>,
        Mauro Carvalho Chehab <mchehab@kernel.org>,
        Tony Luck <tony.luck@intel.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Manish Narani <manish.narani@xilinx.com>,
        Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
        Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>,
        Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
        Punnaiah Choudary Kalluri 
        <punnaiah.choudary.kalluri@xilinx.com>,
        Dinh Nguyen <dinguyen@kernel.org>,
        James Morse <james.morse@arm.com>,
        Robert Richter <rric@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
        Krzysztof Kozlowski <krzk@kernel.org>
Subject: Re: [PATCH 02/13] dt-bindings: memory: snps: Add Baikal-T1 DDRC
 support
Message-ID: <20220909125745.42myr3zwwbfn2tea@mobilestation>
References: <20220822191957.28546-1-Sergey.Semin@baikalelectronics.ru>
 <20220822191957.28546-3-Sergey.Semin@baikalelectronics.ru>
 <20220830180028.GA1758236-robh@kernel.org>
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Hi Rob,
Sorry for missing your message. It has kind of got lost among the
Krzysztof' comments.

On Tue, Aug 30, 2022 at 01:00:28PM -0500, Rob Herring wrote:
> On Mon, Aug 22, 2022 at 10:19:45PM +0300, Serge Semin wrote:
> > Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a
> > with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There
> > are individual IRQs for each ECC and DFI events.The dedicated scrubber
> > clock source is absent since it's fully synchronous to the core clock.
> > In addition to that the DFI-DDR PHY CSRs can be accessed via a separate
> > registers space.
> 

> Are you sure the phy and dfi irq shouldn't be a separate device?

I am sure that the DFI IRQ is a part of the DW uMCTl2 DDR controller
specification. The DFI interface has a special signal called
"dfi_alert_n". It is supposed to be supplied to the DDR controller
from the DDR PHY. The signal state indicates the CRC/Parity errors
detected on the address/command sent to the PHY/SDRAM side. Aside with
some other statuses the signal state is reflected in the DW uMCTL2
CRCPARSTAT register. The CSR state in its turn is then sent out via
the corresponding output wire (dfi_err_int) up to the IRQ controller.
So to speak there is no doubts the DFI errors IRQ is a part of the DW
uMCTL2 DDRC IRQs interface.

Regarding the PHY CSR space. You are right. It is a separate device
indeed. I'll drop the PHY CSR region from here.

-Sergey

> 
> Rob