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Date:   Sat, 10 Sep 2022 12:53:40 +0200
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Subject: Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second
 VPE
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To:     Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc:     Marc Zyngier <maz@kernel.org>,
        Sander Vanheule <sander@svanheule.net>,
        Hauke Mehrtens <hauke@hauke-m.de>, git@birger-koblitz.de,
        linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20220702190705.5319-1-olek2@wp.pl>
 <3c9a032edd0fb9b9608ad3ca08d6e3cc38f21464.camel@svanheule.net>
 <87fsjen2kl.wl-maz@kernel.org> <20220706081901.GA10797@alpha.franken.de>
 <CAFBinCAsj=RNvitj2tXJU6pTLSbanRXdKM9H4vyF=N9N=PP06g@mail.gmail.com>
 <20220707100630.GC9894@alpha.franken.de>
 <CAFBinCBn3+MbKFE84Y0KjW4qG_88+HuBTzRhPQSDqzqGhyhhZw@mail.gmail.com>
 <20220707143930.GA14693@alpha.franken.de>
From:   Aleksander Bajkowski <olek2@wp.pl>
In-Reply-To: <20220707143930.GA14693@alpha.franken.de>
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Hi THomas,

On 7/7/22 16:39, Thomas Bogendoerfer wrote:
[...]
>> Or can you point me to the code in
>> drivers/irqchip/irq-mips-cpu.c that's responsible for enabling the
>> interrupts on VPE 1 (is it simply unmask_mips_irq)?
> 
> IMHO there is the problem, irq-mips-cpu.c can only do CPU irq operations
> on the same CPU. I've checked MIPS MT specs and it's possible do
> modify CP0 registers between VPEs. Using that needs changes in
> irq-mips-cpu.c. But mabye that's not woth the effort as probably
> all SMP cabable platforms have some multi processort capable
> interrupt controller implemented.
> 
> I thought about another way solve the issue. By introducing a
> new function in smp-mt.c which sets the value of the interrupt
> mask for the secondary CPU, which is then used in vsmp_init_secondary().
> Not sure if this is worth the effort compared to a .boot_secondary
> override.


Enabling interrupts on the second VPE using hotplug will be accepted
upstream? Below is a sample patch.

Unfortunately, this is not a generic solution. If in the future there
are more platforms that require a similar patch, this can be converted
into some generic solution.

--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -335,6 +336,18 @@ static const struct irq_domain_ops irq_domain_ops = {
 	.map = icu_map,
 };
 
+static int lantiq_cpu_starting(unsigned int cpu)
+{
+	/*
+	 * MIPS CPU startup function vsmp_init_secondary() will only enable some of
+	 *  the interrupts for the second CPU/VPE. Fix this during hotplug.
+	 */
+	if (cpu > 0)
+		set_c0_status(ST0_IM);
+
+	return 0;
+}
+
 int __init icu_of_init(struct device_node *node, struct device_node *parent)
 {
 	struct device_node *eiu_node;
@@ -410,6 +423,10 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
 	}
 	of_node_put(eiu_node);
 
+	cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LANTIQ_STARTING,
+				  "arch/mips/lantiq:starting",
+				  lantiq_cpu_starting, NULL);
+
 	return 0;
 }
 
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -152,6 +152,7 @@ enum cpuhp_state {
 	CPUHP_AP_IRQ_RISCV_STARTING,
 	CPUHP_AP_IRQ_LOONGARCH_STARTING,
 	CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
+	CPUHP_AP_IRQ_LANTIQ_STARTING,
 	CPUHP_AP_ARM_MVEBU_COHERENCY,
 	CPUHP_AP_MICROCODE_LOADER,
 	CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING,


Best regards,
Aleksander