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From:   =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
To:     Thierry Reding <thierry.reding@gmail.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Rob Herring <robh@kernel.org>,
        =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= <kw@linux.com>,
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        Jonathan Hunter <jonathanh@nvidia.com>
Cc:     linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: [PATCH] PCI: tegra: Update comment about config space
Date:   Sun, 11 Sep 2022 13:32:16 +0200
Message-Id: <20220911113216.14892-1-pali@kernel.org>
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Like many other ARM PCIe controllers, it uses old PCI Configuration
Mechanism #1 from PCI Local Bus for accessing PCI config space.
It is not PCIe ECAM in any case.

Signed-off-by: Pali Rohár <pali@kernel.org>
---
 drivers/pci/controller/pci-tegra.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 8e323e93be91..5df90d183526 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -395,9 +395,11 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
 }
 
 /*
- * The configuration space mapping on Tegra is somewhat similar to the ECAM
- * defined by PCIe. However it deviates a bit in how the 4 bits for extended
- * register accesses are mapped:
+ * The configuration space mapping on Tegra is somewhat similar to the Intel
+ * PCI Configuration Mechanism #1 as defined in PCI Local Bus Specification.
+ * But it is mapped directly into physical address space as opposite of the
+ * CF8/CFC indirect access, bit 31 (enable) is unset and reserved bits [27:24]
+ * are used to access extended PCIe config space registers.
  *
  *    [27:24] extended register number
  *    [23:16] bus number
-- 
2.20.1