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Date:   Mon, 12 Sep 2022 16:02:34 +0200
From:   Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To:     Aleksander Bajkowski <olek2@wp.pl>
Cc:     Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
        Marc Zyngier <maz@kernel.org>,
        Sander Vanheule <sander@svanheule.net>,
        Hauke Mehrtens <hauke@hauke-m.de>, git@birger-koblitz.de,
        linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second
 VPE
Message-ID: <20220912140233.GA9366@alpha.franken.de>
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On Sat, Sep 10, 2022 at 12:53:40PM +0200, Aleksander Bajkowski wrote:
> Hi THomas,
> 
> On 7/7/22 16:39, Thomas Bogendoerfer wrote:
> [...]
> >> Or can you point me to the code in
> >> drivers/irqchip/irq-mips-cpu.c that's responsible for enabling the
> >> interrupts on VPE 1 (is it simply unmask_mips_irq)?
> > 
> > IMHO there is the problem, irq-mips-cpu.c can only do CPU irq operations
> > on the same CPU. I've checked MIPS MT specs and it's possible do
> > modify CP0 registers between VPEs. Using that needs changes in
> > irq-mips-cpu.c. But mabye that's not woth the effort as probably
> > all SMP cabable platforms have some multi processort capable
> > interrupt controller implemented.
> > 
> > I thought about another way solve the issue. By introducing a
> > new function in smp-mt.c which sets the value of the interrupt
> > mask for the secondary CPU, which is then used in vsmp_init_secondary().
> > Not sure if this is worth the effort compared to a .boot_secondary
> > override.
> 
> 
> Enabling interrupts on the second VPE using hotplug will be accepted
> upstream? Below is a sample patch.

as this is just another hack, below is what I prefer.

Thomas.

commit 15853dc9e6d213558acbf961f98e9f77b4b61db2
Author: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Date:   Mon Sep 12 15:59:44 2022 +0200

    my lantiq approach

diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index c731082a0c42..1cc4f56b57f6 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -84,6 +84,16 @@ void __init plat_mem_setup(void)
 	__dt_setup_arch(dtb);
 }
 
+#if defined(CONFIG_MIPS_MT_SMP)
+extern const struct plat_smp_ops vsmp_smp_ops;
+static struct plat_smp_ops lantiq_smp_ops;
+
+static void lantiq_init_secondary(void)
+{
+	set_c0_status(ST0_IM);
+}
+#endif
+
 void __init prom_init(void)
 {
 	/* call the soc specific detetcion code and get it to fill soc_info */
@@ -95,7 +105,13 @@ void __init prom_init(void)
 	prom_init_cmdline();
 
 #if defined(CONFIG_MIPS_MT_SMP)
-	if (register_vsmp_smp_ops())
+
+	if (cpu_has_mipsmt) {
+		lantiq_smp_ops = vsmp_smp_ops;
+		lantiq_smp_ops.init_secondary = lantiq_init_secondary;
+		register_smp_ops(&lantiq_smp_ops);
+	} else {
 		panic("failed to register_vsmp_smp_ops()");
+	}
 #endif
 }

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]