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Date:   Mon, 12 Sep 2022 09:20:48 -0500
From:   Rob Herring <robh@kernel.org>
To:     Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Michal Simek <michal.simek@xilinx.com>,
        Borislav Petkov <bp@alien8.de>,
        Mauro Carvalho Chehab <mchehab@kernel.org>,
        Tony Luck <tony.luck@intel.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Manish Narani <manish.narani@xilinx.com>,
        Serge Semin <fancer.lancer@gmail.com>,
        Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
        Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>,
        Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
        Punnaiah Choudary Kalluri 
        <punnaiah.choudary.kalluri@xilinx.com>,
        Dinh Nguyen <dinguyen@kernel.org>,
        James Morse <james.morse@arm.com>,
        Robert Richter <rric@kernel.org>, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org,
        linux-kernel@vger.kernel.org, Krzysztof Kozlowski <krzk@kernel.org>
Subject: Re: [PATCH v2 02/15] dt-bindings: memory: snps: Extend schema with
 IRQs/resets/clocks props
Message-ID: <20220912142048.GB1170702-robh@kernel.org>
References: <20220910195659.11843-1-Sergey.Semin@baikalelectronics.ru>
 <20220910195659.11843-3-Sergey.Semin@baikalelectronics.ru>
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In-Reply-To: <20220910195659.11843-3-Sergey.Semin@baikalelectronics.ru>
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On Sat, Sep 10, 2022 at 10:56:46PM +0300, Serge Semin wrote:
> First of all the DW uMCTL2 DDRC IP-core supports the individual IRQ lines
> for each standard event: ECC Corrected Error, ECC Uncorrected Error, ECC
> Address Protection, Scrubber-Done signal, DFI Parity/CRC Error. It's
> possible that the platform engineers merge them up in the IRQ controller
> level. So let's add both configuration support to the DT-schema.
> 
> Secondly the DW uMCTL2 DDRC IP-core can have clock sources like APB
> reference clock, AXI-ports clock, main DDRC core reference clock and
> Scrubber low-power clock. In addition to that each clock domain can have a
> dedicated reset signal. Let's add the properties for at least the denoted
> clock sources and the corresponding reset controls.
> 
> Note the IRQs and the phandles order is deliberately not fixed since some
> of the sources may be absent depending on the IP-core synthesize
> parameters and the particular platform setups.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> 
> ---
> 
> Changelog v2:
> - Replace "snps,ddrc-3.80a" compatible string with "snps,dw-umctl2-ddrc"
>   in the example.
> - Move unrelated changes in to the dedicated patches. (@Krzysztof)
> - Use the IRQ macros in the example. (@Krzysztof)
> ---
>  .../snps,dw-umctl2-ddrc.yaml                  | 61 ++++++++++++++++++-
>  1 file changed, 60 insertions(+), 1 deletion(-)

Reviewed-by: Rob Herring <robh@kernel.org>