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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5276.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 19330053-72be-428a-64a8-08da95360018 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Sep 2022 03:13:58.7936 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XS0JMO/dDFRK5gmCND0EAX7Mn1iCW9mZw2CMKI3JXm32W9DD71axn8Ht+w+LsyLVzmWoq3rqV1yE8bYyOTb2/w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR11MB5139 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Lu Baolu > Sent: Monday, September 12, 2022 10:48 AM >=20 > Previously PASID supports on both IOMMU and PCI devices are enabled in > the > iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA) path. It's > functionally > correct as the SVA is the only feature that requires PASID setup. However= , > looking ahead, we will add more features that need to enable pasid (for > example, kernel DMA with PASID, SIOV, VM guest SVA, etc.). It makes more > sense to enable PASID during iommu probing device. >=20 > This enables PASID during iommu probing device and deprecates the > intel_iommu_enable_pasid() helper. This is safe because the IOMMU > hardware > will block any PCI TLP with a PASID prefix if there is no IOMMU domain > attached to the PASID of the device. >=20 IMHO it's better to enable something only when it's actually required, e.g. does it make more sense to have a IOMMU_DEV_FEAT_PASID instead? What this patch does has one problem. It's an intel-iommu driver internal policy. How can a device driver reliably tell that the pasid capability has been enabled by the iommu driver? Thanks Kevin