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From:   <Conor.Dooley@microchip.com>
To:     <zong.li@sifive.com>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>,
        <paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
        <greentime.hu@sifive.com>, <ben.dooks@sifive.com>, <bp@alien8.de>,
        <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
        <linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 7/7] riscv: Add cache information in AUX vector
Thread-Topic: [PATCH v5 7/7] riscv: Add cache information in AUX vector
Thread-Index: AQHYxzi8Jbge1xGIPUuqsebcZoFnIK3dKm4A
Date:   Tue, 13 Sep 2022 10:34:44 +0000
Message-ID: <88298aa6-6786-12a7-8559-2b49ee1081e2@microchip.com>
References: <20220913061817.22564-1-zong.li@sifive.com>
 <20220913061817.22564-8-zong.li@sifive.com>
In-Reply-To: <20220913061817.22564-8-zong.li@sifive.com>
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