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[2620:137:e000::1:20]) by mx.google.com with ESMTP id c8-20020a50d648000000b00450e9be0e3csi9380943edj.410.2022.09.13.09.23.17; Tue, 13 Sep 2022 09:23:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=u7f1l0lj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235386AbiIMPGa (ORCPT + 99 others); Tue, 13 Sep 2022 11:06:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235431AbiIMPE0 (ORCPT ); Tue, 13 Sep 2022 11:04:26 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07AF3696F4 for ; Tue, 13 Sep 2022 07:30:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 4930ECE10F7 for ; Tue, 13 Sep 2022 14:12:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9E71EC433B5; Tue, 13 Sep 2022 14:12:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663078359; bh=r8wZQgEU+vYFVvB3qrIiAUKrIbQ4wzYX48wo3aj1TWQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=u7f1l0ljeHlbk+AuvmhAWZYSR4O/PDNy/x9v5Dyk+RXo+jSShkYR1CKxKBVxPtrYn Pxcmb9oNHyB9tGaoeqLmaox4wvqcSwVjvoiwYGp6Awg+4nPfOSJPJyq+yOM5J+teDD xJtoDkkDHqzTLbcayVpC5LDiDvhlMyE+7zlp+9c7JF+gPlzWXojvrVnEAg7lOXdUEZ /69I5hmeCAejVwBxeT6pEm8vJRxqhZCDH3FBFrfM8pYli494dJZI5pDGk0h1uuFrUh GgyzYWxkiIND2SG5NhgnCqssy9w5RPc9vwjoNWtHUVBbeEabWQzFO24hzaWt2a0ENz XOZOhuT/MViUQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oY6eT-009x4S-Cs; Tue, 13 Sep 2022 15:12:37 +0100 Date: Tue, 13 Sep 2022 15:12:36 +0100 Message-ID: <8735cvuzvv.wl-maz@kernel.org> From: Marc Zyngier To: Kunkun Jiang Cc: Mark Rutland , "Daniel Lezcano" , Thomas Gleixner , Oliver Upton , , , , Subject: Re: [PATCH] arm64: arch_timer: Fix the lack of set_next_event* for workaround of Cortex-A73 erratum 858921 In-Reply-To: <20220913104723.332-1-jiangkunkun@huawei.com> References: <20220913104723.332-1-jiangkunkun@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: jiangkunkun@huawei.com, mark.rutland@arm.com, daniel.lezcano@linaro.org, tglx@linutronix.de, oupton@google.com, wanghaibin.wang@huawei.com, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 13 Sep 2022 11:47:23 +0100, Kunkun Jiang wrote: > > The patch a38b71b0833e moves the programming of the timers from > the countdown timer (TVAL) over to the comparator (CVAL). This > makes it necessary to read the counter when setting next event. > However, the workaround of Cortex-A73 erratum 858921 does not > set the corresponding set_next_event_phys and set_next_event_virt. > This patch fixes it. > > Fixes: a38b71b0833e ("clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL") > Signed-off-by: Kunkun Jiang > --- > drivers/clocksource/arm_arch_timer.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c > index 9ab8221ee3c6..ff935efb6a88 100644 > --- a/drivers/clocksource/arm_arch_timer.c > +++ b/drivers/clocksource/arm_arch_timer.c > @@ -473,6 +473,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { > .desc = "ARM erratum 858921", > .read_cntpct_el0 = arm64_858921_read_cntpct_el0, > .read_cntvct_el0 = arm64_858921_read_cntvct_el0, > + .set_next_event_phys = erratum_set_next_event_phys, > + .set_next_event_virt = erratum_set_next_event_virt, > }, > #endif > #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1 With the fixed commit message as suggested by Oliver, and a subject more conform to the style of previous commits (something like: "clocksource/drivers/arm_arch_timer: Fix handling of ARM erratum 85821"): Acked-by: Marc Zyngier Daniel, I assume you'll pick this? Thanks, M. -- Without deviation from the norm, progress is not possible.