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Date:   Wed, 14 Sep 2022 11:20:04 -0500
From:   Rob Herring <robh@kernel.org>
To:     Siddharth Vadapalli <s-vadapalli@ti.com>
Cc:     davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
        pabeni@redhat.com, krzysztof.kozlowski@linaro.org,
        krzysztof.kozlowski+dt@linaro.org, linux@armlinux.org.uk,
        vladimir.oltean@nxp.com, grygorii.strashko@ti.com, vigneshr@ti.com,
        nsekhar@ti.com, netdev@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        kishon@ti.com
Subject: Re: [PATCH 1/8] dt-bindings: net: ti: k3-am654-cpsw-nuss: Update
 bindings for J721e CPSW9G
Message-ID: <20220914162004.GA2433106-robh@kernel.org>
References: <20220914095053.189851-1-s-vadapalli@ti.com>
 <20220914095053.189851-2-s-vadapalli@ti.com>
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On Wed, Sep 14, 2022 at 03:20:46PM +0530, Siddharth Vadapalli wrote:
> Update bindings for TI K3 J721e SoC which contains 9 ports (8 external
> ports) CPSW9G module and add compatible for it.
> 
> Changes made:
>     - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G.
>     - Extend pattern properties for new compatible.
>     - Change maximum number of CPSW ports to 8 for new compatible.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>  .../bindings/net/ti,k3-am654-cpsw-nuss.yaml   | 23 +++++++++++++++++--
>  1 file changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
> index 821974815dec..868b7fb58b06 100644
> --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
> +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
> @@ -57,6 +57,7 @@ properties:
>        - ti,am654-cpsw-nuss
>        - ti,j7200-cpswxg-nuss
>        - ti,j721e-cpsw-nuss
> +      - ti,j721e-cpswxg-nuss
>        - ti,am642-cpsw-nuss
>  
>    reg:
> @@ -111,7 +112,7 @@ properties:
>          const: 0
>  
>      patternProperties:
> -      "^port@[1-4]$":
> +      "^port@[1-8]$":
>          type: object
>          description: CPSWxG NUSS external ports
>  
> @@ -121,7 +122,7 @@ properties:
>          properties:
>            reg:
>              minimum: 1
> -            maximum: 4
> +            maximum: 8
>              description: CPSW port number
>  
>            phys:
> @@ -181,6 +182,21 @@ required:
>    - '#size-cells'
>  
>  allOf:
> +  - if:
> +      not:
> +        properties:
> +          compatible:
> +            contains:
> +              const: ti,j721e-cpswxg-nuss
> +    then:
> +      properties:
> +        ethernet-ports:
> +          patternProperties:
> +            "^port@[5-8]$": false
> +            properties:
> +              reg:
> +                maximum: 4

Your indentation is off. 'properties' here is under patternProperties 
making it a DT property.

> +
>    - if:
>        not:
>          properties:
> @@ -192,6 +208,9 @@ allOf:
>          ethernet-ports:
>            patternProperties:
>              "^port@[3-4]$": false
> +            properties:
> +              reg:
> +                maximum: 2

Same here.

>  
>  additionalProperties: false
>  
> -- 
> 2.25.1
> 
> 
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