Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Han Xu <han.xu@nxp.com>
To:     Abel Vesa <abelvesa@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        linux-clk@vger.kernel.org (open list:NXP i.MX CLOCK DRIVERS),
        linux-arm-kernel@lists.infradead.org (moderated list:ARM/FREESCALE IMX
        / MXC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list)
Cc:     miquel.raynal@bootlin.com, linux-mtd@lists.infradead.org,
        han.xu@nxp.com
Subject: [PATCH] clk: imx: imx6sx: remove the SET_RATE_PARENT flag for QSPI clocks
Date:   Wed, 14 Sep 2022 15:10:49 -0500
Message-Id: <20220914201049.3508104-2-han.xu@nxp.com>
In-Reply-To: <20220914201049.3508104-1-han.xu@nxp.com>
References: <20220914201049.3508104-1-han.xu@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?1Wz9L3j3Bx/ZisUPNmQBRxA4+HlKSc6wBx8cnzEdSANvbiNOYA7NKzWgGjdo?=
 =?us-ascii?Q?uLk6cmyCtTwFqT4E8sQDjS2og62apg5xwPcEVdDtIG2j/eWKupsiWayGwKit?=
 =?us-ascii?Q?9x+DcehuIKBNuoJ6fYB5Gpw8ubaIucuVZkCIJ3oV57NKgT+0IAlozHrAmRNV?=
 =?us-ascii?Q?B9oHaRMGA30GX0XtAzjRbRbnI8t1wF0KLTwdYyq/dnrqqoCXv41HM7dKVJpP?=
 =?us-ascii?Q?ePlzCQWEgxYO6R4Kb+kQ3BbWRrhoAJrYvOOq6ShppGVNSCWtvpE4AL3BjwN+?=
 =?us-ascii?Q?WUaTD6+YjuJZWv3GcfXDErBw3MjfY91295eFctIoGwC2HUOhZDWMF54tuFxZ?=
 =?us-ascii?Q?CRhsNRyFqIWdCL7GxuepyS8+Ga1gq5vjie3X1Npw+7erkVE/7ju99RPjJalr?=
 =?us-ascii?Q?MJSlLEDL0BDbt3EDu+J3d8cgzG9wvgB8uIef0EZ8KgzoqYsg/BvGum9Yvnyk?=
 =?us-ascii?Q?l2HjoXHJQagHBgnM+6aNmZdpjn0DiYNemajDuloOjaMY6DleXlU2RXSeCgFq?=
 =?us-ascii?Q?lJnDBkOpbbCkqoiazT4O3L41sB9H3e34qj6J2550hIn99aXIHMPBXvXpV5LE?=
 =?us-ascii?Q?SrmCw8d66qvbjMjnGuSVcdjuKsWIBK7HaCGoI+07w/HNebel5cer+r6LrngV?=
 =?us-ascii?Q?EgocmuIsBX/MO9O2PZkql+Z612LCHQH7EiShjXluH0/CJqmYmZZPia52Gi/f?=
 =?us-ascii?Q?XGGpKFXZhWEcGQbxhrbQscLFJBzmEZoA+p1uCh/EazMaZXMfhlKbwePOdngl?=
 =?us-ascii?Q?Zw6Bi7UzKvtnurhhWjHTnAmdelfjOBbe+rxxcH6IEA5QK8PcfQ+B4XYcBbT4?=
 =?us-ascii?Q?pVnZe0Qc029rzyLm0yZQul3SUaQRfdyYVN45Cnx8VnMIJYIuN8AxeMr9423H?=
 =?us-ascii?Q?xyec4dAg8g8lKr+xSh5BvsLHK7Dy31/RtFC8r3OKC4ycE/hAwLYrppZclz79?=
 =?us-ascii?Q?BW6zNv7xBpxdnP7GyDWvRAfeAESI89PiKSBimdB9t+9MOIxeefP6pOp3QR3s?=
 =?us-ascii?Q?Rl34dxs2MnI/V9GLy57Iy7fCoQJmEOScLIU2h4dDQ7zD3uPdlJDAeWN+QaCg?=
 =?us-ascii?Q?QlHnSgKZ4e5pn70SfNBPxdXFg4mUlj4Rg7Qpw3TkYwwySXjlGSX65PdlJGo7?=
 =?us-ascii?Q?oVsivtgfOViPtlVseaAd3XazAtDyEm93rBlWtqM+ECvn6e3z9jzCPH5uerS2?=
 =?us-ascii?Q?1BDkesMC0j06RXPnm5fFnYX+xUdJ7poIm14lz1/Ul8Qa8Exi6Uj4Z9hA8aFx?=
 =?us-ascii?Q?WSr4uSBzD91DN5RdTYJzEyBeVdQxbf+CnK25qWUJ7ObViM5DQPly95UnHqWm?=
 =?us-ascii?Q?CD4WAsuzQilllze4Kh1t3461eNHdMkmyxGEsi+yT5sHdBddGEThnca4uwwWc?=
 =?us-ascii?Q?GGAmuAluPhsUlJpwXdTyhIWR+3Jilz05qMKBYU6GMW9p9ghYTpqDgSUVZEdg?=
 =?us-ascii?Q?bZIb6XWO6JgWmuRXxm4rHoO/6wQdR1bz9X7DYN6Mp+U0b/C+cAMA++0qg0B0?=
 =?us-ascii?Q?ZOQvgB+j791d5N784OgtcmBQxPpfsHkCACzOsUmR6C1IDGtknSDXTC3SSIj9?=
 =?us-ascii?Q?g8XfsFvRdl3gpWa2KQg=3D?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 81c1cf87-ac9c-43ef-53a3-08da968d485d
X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8781.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2022 20:11:17.6227
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: RfstvbWBJUqKHop0L34jgGD1nFkvW12bOBhXh0Y6IPz898LqE4jDXaIYpqOecu18
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8249
X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,
        RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE
        autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

There is no dedicate parent clock for QSPI so SET_RATE_PARENT flag
should not be used. For instance, the default parent clock for QSPI is
pll2_bus, which is also the parent clock for quite a few modules, such
as MMDC, once GPMI NAND set clock rate for EDO5 mode can cause system
hang due to pll2_bus rate changed.

Fixes: f1541e15e38e ("clk: imx6sx: Switch to clk_hw based API")
Signed-off-by: Han Xu <han.xu@nxp.com>
---
 drivers/clk/imx/clk-imx6sx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index 2301d8fb8c76..1e53e366cde7 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -324,13 +324,13 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 	hws[IMX6SX_CLK_SSI3_SEL]           = imx_clk_hw_mux("ssi3_sel",         base + 0x1c,  14,     2,      ssi_sels,          ARRAY_SIZE(ssi_sels));
 	hws[IMX6SX_CLK_SSI2_SEL]           = imx_clk_hw_mux("ssi2_sel",         base + 0x1c,  12,     2,      ssi_sels,          ARRAY_SIZE(ssi_sels));
 	hws[IMX6SX_CLK_SSI1_SEL]           = imx_clk_hw_mux("ssi1_sel",         base + 0x1c,  10,     2,      ssi_sels,          ARRAY_SIZE(ssi_sels));
-	hws[IMX6SX_CLK_QSPI1_SEL]          = imx_clk_hw_mux_flags("qspi1_sel", base + 0x1c,  7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels), CLK_SET_RATE_PARENT);
+	hws[IMX6SX_CLK_QSPI1_SEL]          = imx_clk_hw_mux("qspi1_sel",        base + 0x1c,  7,      3,      qspi1_sels,        ARRAY_SIZE(qspi1_sels);
 	hws[IMX6SX_CLK_PERCLK_SEL]         = imx_clk_hw_mux("perclk_sel",       base + 0x1c,  6,      1,      perclk_sels,       ARRAY_SIZE(perclk_sels));
 	hws[IMX6SX_CLK_VID_SEL]            = imx_clk_hw_mux("vid_sel",          base + 0x20,  21,     3,      vid_sels,          ARRAY_SIZE(vid_sels));
 	hws[IMX6SX_CLK_ESAI_SEL]           = imx_clk_hw_mux("esai_sel",         base + 0x20,  19,     2,      audio_sels,        ARRAY_SIZE(audio_sels));
 	hws[IMX6SX_CLK_CAN_SEL]            = imx_clk_hw_mux("can_sel",          base + 0x20,  8,      2,      can_sels,          ARRAY_SIZE(can_sels));
 	hws[IMX6SX_CLK_UART_SEL]           = imx_clk_hw_mux("uart_sel",         base + 0x24,  6,      1,      uart_sels,         ARRAY_SIZE(uart_sels));
-	hws[IMX6SX_CLK_QSPI2_SEL]          = imx_clk_hw_mux_flags("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT);
+	hws[IMX6SX_CLK_QSPI2_SEL]          = imx_clk_hw_mux("qspi2_sel",        base + 0x2c,  15,     3,      qspi2_sels,        ARRAY_SIZE(qspi2_sels);
 	hws[IMX6SX_CLK_SPDIF_SEL]          = imx_clk_hw_mux("spdif_sel",        base + 0x30,  20,     2,      audio_sels,        ARRAY_SIZE(audio_sels));
 	hws[IMX6SX_CLK_AUDIO_SEL]          = imx_clk_hw_mux("audio_sel",        base + 0x30,  7,      2,      audio_sels,        ARRAY_SIZE(audio_sels));
 	hws[IMX6SX_CLK_ENET_PRE_SEL]       = imx_clk_hw_mux("enet_pre_sel",     base + 0x34,  15,     3,      enet_pre_sels,     ARRAY_SIZE(enet_pre_sels));
-- 
2.25.1