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Date:   Thu, 15 Sep 2022 12:58:53 +0530
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Subject: Re: [PATCH 1/8] dt-bindings: net: ti: k3-am654-cpsw-nuss: Update
 bindings for J721e CPSW9G
Content-Language: en-US
To:     Rob Herring <robh@kernel.org>
References: <20220914095053.189851-1-s-vadapalli@ti.com>
 <20220914095053.189851-2-s-vadapalli@ti.com>
 <20220914162004.GA2433106-robh@kernel.org>
From:   Siddharth Vadapalli <s-vadapalli@ti.com>
In-Reply-To: <20220914162004.GA2433106-robh@kernel.org>
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Hello Rob,

On 14/09/22 21:50, Rob Herring wrote:
> On Wed, Sep 14, 2022 at 03:20:46PM +0530, Siddharth Vadapalli wrote:
>> Update bindings for TI K3 J721e SoC which contains 9 ports (8 external
>> ports) CPSW9G module and add compatible for it.
>>
>> Changes made:
>>     - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G.
>>     - Extend pattern properties for new compatible.
>>     - Change maximum number of CPSW ports to 8 for new compatible.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> ---
>>  .../bindings/net/ti,k3-am654-cpsw-nuss.yaml   | 23 +++++++++++++++++--
>>  1 file changed, 21 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
>> index 821974815dec..868b7fb58b06 100644
>> --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
>> +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
>> @@ -57,6 +57,7 @@ properties:
>>        - ti,am654-cpsw-nuss
>>        - ti,j7200-cpswxg-nuss
>>        - ti,j721e-cpsw-nuss
>> +      - ti,j721e-cpswxg-nuss
>>        - ti,am642-cpsw-nuss
>>  
>>    reg:
>> @@ -111,7 +112,7 @@ properties:
>>          const: 0
>>  
>>      patternProperties:
>> -      "^port@[1-4]$":
>> +      "^port@[1-8]$":
>>          type: object
>>          description: CPSWxG NUSS external ports
>>  
>> @@ -121,7 +122,7 @@ properties:
>>          properties:
>>            reg:
>>              minimum: 1
>> -            maximum: 4
>> +            maximum: 8
>>              description: CPSW port number
>>  
>>            phys:
>> @@ -181,6 +182,21 @@ required:
>>    - '#size-cells'
>>  
>>  allOf:
>> +  - if:
>> +      not:
>> +        properties:
>> +          compatible:
>> +            contains:
>> +              const: ti,j721e-cpswxg-nuss
>> +    then:
>> +      properties:
>> +        ethernet-ports:
>> +          patternProperties:
>> +            "^port@[5-8]$": false
>> +            properties:
>> +              reg:
>> +                maximum: 4
> 
> Your indentation is off. 'properties' here is under patternProperties 
> making it a DT property.
> 
>> +
>>    - if:
>>        not:
>>          properties:
>> @@ -192,6 +208,9 @@ allOf:
>>          ethernet-ports:
>>            patternProperties:
>>              "^port@[3-4]$": false
>> +            properties:
>> +              reg:
>> +                maximum: 2
> 
> Same here.

Thank you for reviewing the patch. Sorry for the indentation errors. I
will fix them in the v2 series.

Regards,
Siddharth.