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From:   Vineet Gupta <vineetg@rivosinc.com>
To:     linux-riscv@lists.infradead.org
Cc:     linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@rivosinc.com>,
        Christoph Muellner <cmuellner@ventanamicro.com>,
        linux@rivosinc.com, Vineet Gupta <vineetg@rivosinc.com>
Subject: [PATCH v2] riscv: ztso: disallow elf binaries needing TSO
Date:   Thu, 15 Sep 2022 21:23:31 -0700
Message-Id: <20220916042331.1398823-1-vineetg@rivosinc.com>
In-Reply-To: <20220916030552.1396820-1-vineetg@rivosinc.com>
References: <20220916030552.1396820-1-vineetg@rivosinc.com>
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As of now the software stack needs work to support ztso. Until that work
is finished, disallow binaries needing TSO.

This patch is needed to help ztso ratification and prolifiration of tso
bits in tooling.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
---
Changes since v1
  - Build error (and boot tested on qemu)
  - Improved the comments a bit
---
 arch/riscv/include/asm/elf.h      | 11 ++++++++++-
 arch/riscv/include/uapi/asm/elf.h |  2 ++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
index f53c40026c7a..b6b4542b3039 100644
--- a/arch/riscv/include/asm/elf.h
+++ b/arch/riscv/include/asm/elf.h
@@ -26,10 +26,19 @@
 
 #define ELF_DATA	ELFDATA2LSB
 
+/*
+ * Make sure the elf being loaded is compatible with extensions.
+ *
+ * In the final incarnation this will get the extension list from DT and
+ * make sure elf can run on given hardware+kernel.
+ * For now disallow TSO built binaries.
+ */
+#define rv_ext_ok(x)	(!((x)->e_flags & EF_RISCV_TSO))
+
 /*
  * This is used to ensure we don't load something for the wrong architecture.
  */
-#define elf_check_arch(x) ((x)->e_machine == EM_RISCV)
+#define elf_check_arch(x) ((x)->e_machine == EM_RISCV && rv_ext_ok(x))
 
 #define CORE_DUMP_USE_REGSET
 #define ELF_EXEC_PAGESIZE	(PAGE_SIZE)
diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h
index d696d6610231..fa9e4c52c7ac 100644
--- a/arch/riscv/include/uapi/asm/elf.h
+++ b/arch/riscv/include/uapi/asm/elf.h
@@ -32,6 +32,8 @@ typedef union __riscv_fp_state elf_fpregset_t;
 #define ELF_RISCV_R_TYPE(r_info)	ELF32_R_TYPE(r_info)
 #endif
 
+#define EF_RISCV_TSO		(1 << 3)
+
 /*
  * RISC-V relocation types
  */
-- 
2.34.1