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Subject: Re: [net-next PATCH 0/4] Add PTP support for CN10K silicon
From:   patchwork-bot+netdevbpf@kernel.org
Message-Id: <166344242177.31603.2337871573726752416.git-patchwork-notify@kernel.org>
Date:   Sat, 17 Sep 2022 19:20:21 +0000
References: <20220910075416.22887-1-naveenm@marvell.com>
In-Reply-To: <20220910075416.22887-1-naveenm@marvell.com>
To:     Naveen Mamindlapalli <naveenm@marvell.com>
Cc:     kuba@kernel.org, davem@davemloft.net, edumazet@google.com,
        pabeni@redhat.com, richardcochran@gmail.com,
        netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
        sgoutham@marvell.com, hkelam@marvell.com
Precedence: bulk

Hello:

This series was applied to netdev/net-next.git (master)
by David S. Miller <davem@davemloft.net>:

On Sat, 10 Sep 2022 13:24:12 +0530 you wrote:
> This patchset adds PTP support for CN10K silicon, specifically
> to workaround few hardware issues and to add 1-step mode.
> 
> Patchset overview:
> 
> Patch #1 returns correct ptp timestamp in nanoseconds captured
>          when external timestamp event occurs.
> 
> [...]

Here is the summary with links:
  - [net-next,1/4] octeontx2-af: return correct ptp timestamp for CN10K silicon
    https://git.kernel.org/netdev/net-next/c/a8025e7946a2
  - [net-next,2/4] octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
    https://git.kernel.org/netdev/net-next/c/2958d17a8984
  - [net-next,3/4] octeontx2-af: Add PTP PPS Errata workaround on CN10K silicon
    https://git.kernel.org/netdev/net-next/c/2ef4e45d99b1
  - [net-next,4/4] octeontx2-af: Initialize PTP_SEC_ROLLOVER register properly
    https://git.kernel.org/netdev/net-next/c/85a5f9638313

You are awesome, thank you!
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