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[2620:137:e000::1:20]) by mx.google.com with ESMTP id w7-20020a637b07000000b004393ad9fdccsi3659174pgc.519.2022.09.19.00.02.58; Mon, 19 Sep 2022 00:03:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=mX4onGwO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229745AbiISGb1 (ORCPT + 99 others); Mon, 19 Sep 2022 02:31:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229483AbiISGbY (ORCPT ); Mon, 19 Sep 2022 02:31:24 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44DF017A94 for ; Sun, 18 Sep 2022 23:31:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663569084; x=1695105084; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NjjJDzk3PCTN6zCJqZ/fLOxb+/E/7A+Bi6Uyy86kecA=; b=mX4onGwOrvxPg2JuXKpXGJz+uQ/TTOnSrHIIXQ0Ga+v1bR3MOWLgT2OV swH/4kTLJLixkZbDjl7VkVkPARsFazGrdC3ZT+nuAeKUgydexTel8Q4fO +9+fiAPfylJb3rEfKWm6g4ejPeHuNPfAxOfgOiQH8iwDPWgROVOfnKCoT nkBMu+9g2LD/KkLasBJEzU9Lfm+XjDsRDEVY4hEk74qh79E3lFij67v3m bFjGjcilVs296TQuNTO98J96SLZTvqq9HIoKkp2IU5g5tIFr821WF8Gpg ozKt5qucZS6olKgQrAN8lDaHv9EJUDy/7RydjycwbfsIb+Hcwk63l3IhC Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10474"; a="279699708" X-IronPort-AV: E=Sophos;i="5.93,327,1654585200"; d="scan'208";a="279699708" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2022 23:31:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,327,1654585200"; d="scan'208";a="680715161" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga008.fm.intel.com with ESMTP; 18 Sep 2022 23:31:22 -0700 From: Lu Baolu To: iommu@lists.linux.dev Cc: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jacob Pan , linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH 1/2] iommu/vt-d: Avoid unnecessary global IRTE cache invalidation Date: Mon, 19 Sep 2022 14:25:22 +0800 Message-Id: <20220919062523.3438951-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919062523.3438951-1-baolu.lu@linux.intel.com> References: <20220919062523.3438951-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some VT-d hardware implementations invalidate all interrupt remapping hardware translation caches as part of SIRTP flow. The VT-d spec adds a ESIRTPS (Enhanced Set Interrupt Remap Table Pointer Support, section 11.4.2 in VT-d spec) capability bit to indicate this. With this bit set, software has no need to issue the global invalidation request. Signed-off-by: Jacob Pan Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.h | 1 + drivers/iommu/intel/irq_remapping.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index eef1a166b855..5407d82df4d1 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -146,6 +146,7 @@ /* * Decoding Capability Register */ +#define cap_esirtps(c) (((c) >> 62) & 1) #define cap_fl5lp_support(c) (((c) >> 60) & 1) #define cap_pi_support(c) (((c) >> 59) & 1) #define cap_fl1gp_support(c) (((c) >> 56) & 1) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c index 2e9683e970f8..b4a91fbd1c2f 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -494,7 +494,8 @@ static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) * Global invalidation of interrupt entry cache to make sure the * hardware uses the new irq remapping table. */ - qi_global_iec(iommu); + if (!cap_esirtps(iommu->cap)) + qi_global_iec(iommu); } static void iommu_enable_irq_remapping(struct intel_iommu *iommu) -- 2.34.1