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Date:   Mon, 19 Sep 2022 01:30:29 -0700
From:   Jerry Snitselaar <jsnitsel@redhat.com>
To:     Lu Baolu <baolu.lu@linux.intel.com>
Cc:     iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
        Will Deacon <will@kernel.org>,
        Robin Murphy <robin.murphy@arm.com>,
        Kevin Tian <kevin.tian@intel.com>,
        Jacob Pan <jacob.jun.pan@linux.intel.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] iommu/vt-d: Avoid unnecessary global DMA cache
 invalidation
Message-ID: <20220919083029.vwwxkm5kuyylgbew@cantor>
References: <20220919062523.3438951-1-baolu.lu@linux.intel.com>
 <20220919062523.3438951-3-baolu.lu@linux.intel.com>
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In-Reply-To: <20220919062523.3438951-3-baolu.lu@linux.intel.com>
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On Mon, Sep 19, 2022 at 02:25:23PM +0800, Lu Baolu wrote:
> Some VT-d hardware implementations invalidate all DMA remapping hardware
> translation caches as part of SRTP flow. The VT-d spec adds a ESRTPS
> (Enhanced Set Root Table Pointer Support, section 11.4.2 in VT-d spec)
> capability bit to indicate this. With this bit set, software has no need
> to issue the global invalidation request.
> 
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>

Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com

> ---
>  drivers/iommu/intel/iommu.h | 1 +
>  drivers/iommu/intel/iommu.c | 7 +++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h
> index 5407d82df4d1..251a609fdce3 100644
> --- a/drivers/iommu/intel/iommu.h
> +++ b/drivers/iommu/intel/iommu.h
> @@ -146,6 +146,7 @@
>  /*
>   * Decoding Capability Register
>   */
> +#define cap_esrtps(c)		(((c) >> 63) & 1)
>  #define cap_esirtps(c)		(((c) >> 62) & 1)
>  #define cap_fl5lp_support(c)	(((c) >> 60) & 1)
>  #define cap_pi_support(c)	(((c) >> 59) & 1)
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 8e5d99197d39..c20f3e060bac 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -1239,6 +1239,13 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
>  
>  	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
>  
> +	/*
> +	 * Hardware invalidates all DMA remapping hardware translation
> +	 * caches as part of SRTP flow.
> +	 */
> +	if (cap_esrtps(iommu->cap))
> +		return;
> +
>  	iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
>  	if (sm_supported(iommu))
>  		qi_flush_pasid_cache(iommu, 0, QI_PC_GLOBAL, 0);
> -- 
> 2.34.1
>