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[98.179.76.75]) by smtp.gmail.com with ESMTPSA id l14-20020ac84cce000000b0034355a352d1sm9779291qtv.92.2022.09.19.01.29.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Sep 2022 01:29:20 -0700 (PDT) Date: Mon, 19 Sep 2022 01:29:19 -0700 From: Jerry Snitselaar To: Lu Baolu Cc: iommu@lists.linux.dev, Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jacob Pan , linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] iommu/vt-d: Avoid unnecessary global IRTE cache invalidation Message-ID: <20220919082919.ekv6p47y2nnmpswk@cantor> References: <20220919062523.3438951-1-baolu.lu@linux.intel.com> <20220919062523.3438951-2-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220919062523.3438951-2-baolu.lu@linux.intel.com> X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Sep 19, 2022 at 02:25:22PM +0800, Lu Baolu wrote: > Some VT-d hardware implementations invalidate all interrupt remapping > hardware translation caches as part of SIRTP flow. The VT-d spec adds > a ESIRTPS (Enhanced Set Interrupt Remap Table Pointer Support, section > 11.4.2 in VT-d spec) capability bit to indicate this. With this bit set, > software has no need to issue the global invalidation request. > > Signed-off-by: Jacob Pan > Signed-off-by: Lu Baolu Reviewed-by: Jerry Snitselaar --- > drivers/iommu/intel/iommu.h | 1 + > drivers/iommu/intel/irq_remapping.c | 3 ++- > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h > index eef1a166b855..5407d82df4d1 100644 > --- a/drivers/iommu/intel/iommu.h > +++ b/drivers/iommu/intel/iommu.h > @@ -146,6 +146,7 @@ > /* > * Decoding Capability Register > */ > +#define cap_esirtps(c) (((c) >> 62) & 1) > #define cap_fl5lp_support(c) (((c) >> 60) & 1) > #define cap_pi_support(c) (((c) >> 59) & 1) > #define cap_fl1gp_support(c) (((c) >> 56) & 1) > diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c > index 2e9683e970f8..b4a91fbd1c2f 100644 > --- a/drivers/iommu/intel/irq_remapping.c > +++ b/drivers/iommu/intel/irq_remapping.c > @@ -494,7 +494,8 @@ static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) > * Global invalidation of interrupt entry cache to make sure the > * hardware uses the new irq remapping table. > */ > - qi_global_iec(iommu); > + if (!cap_esirtps(iommu->cap)) > + qi_global_iec(iommu); > } > > static void iommu_enable_irq_remapping(struct intel_iommu *iommu) > -- > 2.34.1 >