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[2a02:8440:6340:f287:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id cf16-20020a0564020b9000b0044fc3c0930csm20424246edb.16.2022.09.19.09.59.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Sep 2022 09:59:44 -0700 (PDT) From: Guillaume Ranquet Date: Mon, 19 Sep 2022 18:55:59 +0200 Subject: [PATCH v1 01/17] dt-bindings: clk: mediatek: Add MT8195 DPI clocks MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20220919-v1-1-4844816c9808@baylibre.com> References: <20220919-v1-0-4844816c9808@baylibre.com> In-Reply-To: <20220919-v1-0-4844816c9808@baylibre.com> To: Vinod Koul , Stephen Boyd , David Airlie , Rob Herring , Philipp Zabel , Krzysztof Kozlowski , Daniel Vetter , Chunfeng Yun , CK Hu , Jitao shi , Chun-Kuang Hu , Michael Turquette , Kishon Vijay Abraham I , Matthias Brugger Cc: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, Pablo Sun , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Mattijs Korpershoek , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Guillaume Ranquet , devicetree@vger.kernel.org X-Mailer: b4 0.10.0-dev X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pablo Sun Expand dt-bindings slot for VDOSYS1 of MT8195. This clock is required by the DPI1 hardware and is a downstream of the HDMI pixel clock. Signed-off-by: Pablo Sun Signed-off-by: Guillaume Ranquet Reviewed-by: Mattijs Korpershoek diff --git a/include/dt-bindings/clock/mt8195-clk.h b/include/dt-bindings/clock/mt8195-clk.h index 95cf812a0b37..d70d017ad69c 100644 --- a/include/dt-bindings/clock/mt8195-clk.h +++ b/include/dt-bindings/clock/mt8195-clk.h @@ -859,6 +859,8 @@ #define CLK_VDO1_DPINTF 47 #define CLK_VDO1_DISP_MONITOR_DPINTF 48 #define CLK_VDO1_26M_SLOW 49 -#define CLK_VDO1_NR_CLK 50 +#define CLK_VDO1_DPI1_HDMI 50 +#define CLK_VDO1_NR_CLK 51 + #endif /* _DT_BINDINGS_CLK_MT8195_H */ -- b4 0.10.0-dev