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Tue, 20 Sep 2022 00:51:44 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 20 Sep 2022 00:51:44 -0500 Received: from xhdswatia40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Tue, 20 Sep 2022 00:51:21 -0500 From: Sarath Babu Naidu Gaddam To: , , , , CC: , , , , , , , , , , Subject: [RFC V3 PATCH 0/8] Xilinx DMA enhancements and optimization Date: Tue, 20 Sep 2022 11:21:11 +0530 Message-ID: <20220920055119.12634-1-sarath.babu.naidu.gaddam@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT004:EE_|SJ0PR12MB6903:EE_ X-MS-Office365-Filtering-Correlation-Id: 495c86b7-0396-4524-9503-08da9acc338b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2022 05:51:45.3263 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 495c86b7-0396-4524-9503-08da9acc338b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6903 X-Spam-Status: No, score=0.9 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some background about the patch series: Xilinx Axi Ethernet device driver (xilinx_axienet_main.c) currently has axi-dma code inside it. The goal is to refactor axiethernet driver and use existing AXI DMA driver using DMAEngine API. This patchset does feature addition and optimization to support axidma integration with axiethernet network driver. Once axidma version is accepted mcdma specific changes will be added in followup version. Changes for V2: - Use metadata API[1] for passing metadata from dma to netdev client. - Read irq-delay from DT. - Remove desc_callback_valid check. - Addressed RFC v1 comments[2]. - Minor code refactoring. Changes for V3: - Add device_config support for passing any dma client data. - Address RFC v2 comments. - remove hardcoding for axidma_tx_segment. - Below review comment is in pipeline. We are facing a race issue when addressing it. we will fix it in the next version. "chan->idle = true; in xilinx_dma_irq_handler() needs to be gated on the active_list being empty". Comments, suggestions are very welcome Radhey Shyam Pandey (7): dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected property dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client dmaengine: xilinx_dma: Increase AXI DMA transaction segment count dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase dmaengine: xilinx_dma: Program interrupt delay timeout Sarath Babu Naidu Gaddam (1): dmaengine: xilinx_dma: Add device_config support .../bindings/dma/xilinx/xilinx_dma.txt | 4 + drivers/dma/xilinx/xilinx_dma.c | 107 ++++++++++++++++-- include/linux/dma/xilinx_dma.h | 16 +++ 3 files changed, 115 insertions(+), 12 deletions(-) -- 2.25.1