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In-Reply-To: <bfca0379-7346-13e7-a18f-66740c5871b3@linaro.org>
From:   Tomer Maimon <tmaimon77@gmail.com>
Date:   Tue, 20 Sep 2022 10:59:12 +0300
Message-ID: <CAP6Zq1gyDW8ZwwAZ1jyfNEZa09WN-biZZJY8tBmW_gzMzpj3ZA@mail.gmail.com>
Subject: Re: [PATCH v2 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc:     Rob Herring <robh@kernel.org>,
        Avi Fishman <avifishman70@gmail.com>,
        Tali Perry <tali.perry1@gmail.com>,
        Joel Stanley <joel@jms.id.au>,
        Patrick Venture <venture@google.com>,
        Nancy Yuen <yuenn@google.com>,
        Benjamin Fair <benjaminfair@google.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        =?UTF-8?Q?Jonathan_Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>,
        zhengbin13@huawei.com, OpenBMC Maillist <openbmc@lists.ozlabs.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        devicetree <devicetree@vger.kernel.org>
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On Mon, 19 Sept 2022 at 19:06, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 19/09/2022 16:31, Tomer Maimon wrote:
> >>>>> +examples:
> >>>>> +  - |
> >>>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>>> +    #include <dt-bindings/gpio/gpio.h>
> >>>>> +
> >>>>> +    soc {
> >>>>> +      #address-cells = <2>;
> >>>>> +      #size-cells = <2>;
> >>>>> +
> >>>>> +      pinctrl: pinctrl@f0800000 {
> >>>>> +        compatible = "nuvoton,npcm845-pinctrl";
> >>>>> +        ranges = <0x0 0x0 0xf0010000 0x8000>;
> >>>>> +        #address-cells = <1>;
> >>>>> +        #size-cells = <1>;
> >>>>> +        nuvoton,sysgcr = <&gcr>;
> >>>>> +
> >>>>> +        gpio0: gpio@f0010000 {
> >>>>
> >>>> gpio@0
> >>>>
> >>>> Is this really a child block of the pinctrl? Doesn't really look like it
> >>>> based on addressess. Where are the pinctrl registers? In the sysgcr? If
> >>>> so, then pinctrl should be a child of it. But that doesn't really work
> >>>> too well with gpio child nodes...
> >>> the pin controller mux is handled by sysgcr this is why the sysgcr in
> >>> the mother node,
> >>> and the pin configuration are handled by the GPIO registers.  each
> >>> GPIO bank (child) contains 32 GPIO.
> >>> this is why the GPIO is the child node.
> >>
> >> Then maybe pinctrl should be the sysgcr and expose regmap for other devices?
> > The pin controller using the sysgcr to handle the pinmux, this is why
> > the sysgcr is in the mother node, is it problematic?
>
> You said pin-controller mux registers are in sysgcr, so it should not be
> used via syscon.
Sorry but maybe I missed something.
the sysgcr is used for miscellaneous features and not only for the pin
controller mux, this is why it used syscon and defined in the dtsi:
                gcr: system-controller@f0800000 {
                        compatible = "nuvoton,npcm845-gcr", "syscon";
                        reg = <0x0 0xf0800000 0x0 0x1000>;
                };
>
> Please provide address map description to convince us that this is
> correct HW representation.
GCR (sysgcr) registers 0xf0800000-0xf0801000 - used for miscellaneous
features, not only pin mux.
GPIO0 0xf0010000-0xf0011000
GPIO1 0xf0011000-0xf0012000
...
GPIO7 0xf0017000-0xf0018000
>
> Best regards,
> Krzysztof

Best regards,

Tomer