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[2620:137:e000::1:20]) by mx.google.com with ESMTP id a11-20020a17090640cb00b007808393cf7fsi798538ejk.413.2022.09.20.02.52.38; Tue, 20 Sep 2022 02:53:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=JBs016aY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230124AbiITJ3D (ORCPT + 99 others); Tue, 20 Sep 2022 05:29:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230037AbiITJ3B (ORCPT ); Tue, 20 Sep 2022 05:29:01 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 502BE6CD04; Tue, 20 Sep 2022 02:29:00 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E18F661DC6; Tue, 20 Sep 2022 09:28:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53F92C433D6; Tue, 20 Sep 2022 09:28:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663666139; bh=c9tNWaX+fG4Wy0u/MHxZ7+cfWDSAeFQOc1Tp0X/dp30=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=JBs016aYWv/9hPEvaf9RCowNRCwkfgSvgZ7FXp58il6YCQZHRDQdbJ3QF+GokU2rs UrY8lL9GIL3WSxvpcKol9BBH/PxXKlmw228u73oxfTbt68kcD3n2rUF+meD/+brhjf o8135p5R8VrhCW7O8GXaSvR/DkoEPgLvPjA9p7Cwu0bRzGwMsLaKZw2Lgqkd4apvNk /ZGuQbF9NHpTVNihvmN4C+qBWxXcKgL8trBUsYxsbyeXHfObkN3MJYxThz2i/QmIYj z09laYILSS8/AdN0SBWYYjPZL3dGE2NAuUo+KnHdrXwkJfsrXMHs49XTZUZ9c1h8RS qfCzkbC/9pcwQ== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oaZYr-0002Wy-8G; Tue, 20 Sep 2022 11:29:01 +0200 Date: Tue, 20 Sep 2022 11:29:01 +0200 From: Johan Hovold To: Vinod Koul , Manivannan Sadhasivam Cc: andersson@kernel.org, kishon@ti.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers Message-ID: References: <20220910063857.17372-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 20, 2022 at 12:15:56PM +0530, Vinod Koul wrote: > On 10-09-22, 12:08, Manivannan Sadhasivam wrote: > > In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and > > QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2 > > and QPHY_V5_PCS_EQ_CONFIG3. > > > > This causes high latency when ASPM is enabled, so fix it! > > > > Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") > > Signed-off-by: Manivannan Sadhasivam > > --- > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h > > index 61a44519f969..cca6455ec98c 100644 > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h > > @@ -11,7 +11,7 @@ > > #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 > > #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 > > #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 > > -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 > > -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 Why are you removing these defines? (They are correct for sc8280xp.) > > +#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0 > > +#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4 > > This conflicts with c0c7769cdae2 ("phy: qcom-qmp: Add SC8280XP USB3 UNI phy") > > where QPHY_V5_PCS_EQ_CONFIG5 was added as 0x1e0 > > Do we have a different v5 for SM8450 and SC8280XP? I can confirm that the PCS_EQ_CONFIG defines added for sc8280xp matches the vendor's headers for both the combo and USB PHYs. Johan