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Date:   Tue, 20 Sep 2022 10:14:54 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc:     Jacob Pan <jacob.jun.pan@intel.com>,
        Ashok Raj <ashok.raj@intel.com>,
        "Kirill A. Shutemov" <kirill@shutemov.name>,
        Ashok Raj <ashok_raj@linux.intel.com>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>, x86@kernel.org,
        Kostya Serebryany <kcc@google.com>,
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        Rick Edgecombe <rick.p.edgecombe@intel.com>,
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        Joerg Roedel <joro@8bytes.org>
Subject: Re: [PATCHv8 00/11] Linear Address Masking enabling
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On Thu, Sep 15, 2022 at 08:28:58PM +0300, Kirill A. Shutemov wrote:

> @@ -31,7 +33,17 @@ int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_t min, ioasid_t max)
>  	    min == 0 || max < min)
>  		return -EINVAL;
>  
> +	/* Serialize against address tagging enabling */
> +	if (mmap_write_lock_killable(mm))
> +		return -EINTR;
> +
> +	if (!arch_can_alloc_pasid(mm)) {
> +		mmap_write_unlock(mm);
> +		return -EBUSY;
> +	}

This has nothing to do with "allocating pasid"

Rather should be: "is the CPU page table compatible with the IOMMU HW
page table walker"

For this I would rather have a function that queries the format of the
page table under the mm_struct and we have enum values like
INTEL_NORMAL and INTEL_LAM as possible values.

The iommu driver will block incompatible page table formats, and when
it starts up it should assert something that blocks changing the
format.

Jason