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From:   Biju Das <biju.das.jz@bp.renesas.com>
To:     Prabhakar <prabhakar.csengg@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Conor Dooley <conor.dooley@microchip.com>
CC:     Heiko Stuebner <heiko@sntech.de>,
        Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
        Atish Patra <atishp@rivosinc.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "linux-renesas-soc@vger.kernel.org" 
        <linux-renesas-soc@vger.kernel.org>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: RE: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes
Thread-Topic: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes
Thread-Index: AQHYzSHUiYFQxotF30GY+2sg2SrZHa3oru6A
Date:   Tue, 20 Sep 2022 19:21:46 +0000
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Hi Prabhakar,

Thanks for the patch.

> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>=20
> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
>=20
> This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier
> board DTSIs([0] and [1]).

Just a question,=20

Why can't we reuse SoC dtsi as well, as 90% of the SoC nodes are same?

Split common stuff from arch/arm/boot/dts/renesas/r9a07g043.dtsi=20

and add ARM specific CPU, IRQ to arch/arm/boot/dts/renesas/r9a07g043u.dtsi

RISC-V specific CPU, IRQ to arch/riscv/boot/dts/renesas/r9a07g043f.dtsi

Both r9a07g043{u,f} dtsi will add common dtsi.


Cheers,
Biju


>=20
> As the RZ/G2UL SMARC EVK enables almost all the blocks supported by
> the SoC and whereas for the RZ/Five SMARC EVK we will gradually be
> enabling the blocks as a result we are adding the placeholder nodes to
> avoid DTB compilation errors (currently we dont have support in DTC to
> delete the reference nodes without actual nodes).
>=20
> [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
>=20
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3 -> v4
> * Dropped status and reg-names properties
> * Updated the commit message
> * Note sbc node is not enabled in RZ/G2UL SMARC EVK but will be soon
>   enabled so added a placeholder for this too.
>=20
> v2 -> v3
> * New patch
> ---
>  arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 150
> +++++++++++++++++++++
>  1 file changed, 150 insertions(+)
>=20
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> index fb6733f3cc2b..d90d263b1b13 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -13,6 +13,14 @@ / {
>  	#address-cells =3D <2>;
>  	#size-cells =3D <2>;
>=20
> +	audio_clk1: audio1-clk {
> +		/* placeholder */
> +	};
> +
> +	audio_clk2: audio2-clk {
> +		/* placeholder */
> +	};
> +
>  	cpus {
>  		#address-cells =3D <1>;
>  		#size-cells =3D <0>;
> @@ -54,6 +62,19 @@ soc: soc {
>  		#size-cells =3D <2>;
>  		ranges;
>=20
> +		ssi1: ssi@1004a000 {
> +			reg =3D <0 0x1004a000 0 0x400>;
> +			#sound-dai-cells =3D <0>;
> +
> +			/* placeholder */
> +		};
> +
> +		spi1: spi@1004b000 {
> +			reg =3D <0 0x1004b000 0 0x400>;
> +
> +			/* placeholder */
> +		};
> +
>  		scif0: serial@1004b800 {
>  			compatible =3D "renesas,scif-r9a07g043",
>  				     "renesas,scif-r9a07g044";
> @@ -73,6 +94,41 @@ scif0: serial@1004b800 {
>  			status =3D "disabled";
>  		};
>=20
> +		canfd: can@10050000 {
> +			reg =3D <0 0x10050000 0 0x8000>;
> +
> +			/* placeholder */
> +		};
> +
> +		i2c0: i2c@10058000 {
> +			reg =3D <0 0x10058000 0 0x400>;
> +			#address-cells =3D <1>;
> +			#size-cells =3D <0>;
> +			/* placeholder */
> +		};
> +
> +		i2c1: i2c@10058400 {
> +			reg =3D <0 0x10058400 0 0x400>;
> +			#address-cells =3D <1>;
> +			#size-cells =3D <0>;
> +
> +			/* placeholder */
> +		};
> +
> +		adc: adc@10059000 {
> +			reg =3D <0 0x10059000 0 0x400>;
> +
> +			/* placeholder */
> +		};
> +
> +		sbc: spi@10060000 {
> +			reg =3D <0 0x10060000 0 0x10000>,
> +			      <0 0x20000000 0 0x10000000>,
> +			      <0 0x10070000 0 0x10000>;
> +
> +			/* placeholder */
> +		};
> +
>  		cpg: clock-controller@11010000 {
>  			compatible =3D "renesas,r9a07g043-cpg";
>  			reg =3D <0 0x11010000 0 0x10000>;
> @@ -104,6 +160,82 @@ pinctrl: pinctrl@11030000 {
>  				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
>  		};
>=20
> +		sdhi0: mmc@11c00000 {
> +			reg =3D <0x0 0x11c00000 0 0x10000>;
> +
> +			/* placeholder */
> +		};
> +
> +		sdhi1: mmc@11c10000 {
> +			reg =3D <0x0 0x11c10000 0 0x10000>;
> +
> +			/* placeholder */
> +		};
> +
> +		eth0: ethernet@11c20000 {
> +			reg =3D <0 0x11c20000 0 0x10000>;
> +			#address-cells =3D <1>;
> +			#size-cells =3D <0>;
> +
> +			/* placeholder */
> +		};
> +
> +		eth1: ethernet@11c30000 {
> +			reg =3D <0 0x11c30000 0 0x10000>;
> +			#address-cells =3D <1>;
> +			#size-cells =3D <0>;
> +
> +			/* placeholder */
> +		};
> +
> +		phyrst: usbphy-ctrl@11c40000 {
> +			reg =3D <0 0x11c40000 0 0x10000>;
> +
> +			/* placeholder */
> +		};
> +
> +		ohci0: usb@11c50000 {
> +			reg =3D <0 0x11c50000 0 0x100>;
> +
> +			/* placeholder */
> +		};
> +
> +		ohci1: usb@11c70000 {
> +			reg =3D <0 0x11c70000 0 0x100>;
> +
> +			/* placeholder */
> +		};
> +
> +		ehci0: usb@11c50100 {
> +			reg =3D <0 0x11c50100 0 0x100>;
> +
> +			/* placeholder */
> +		};
> +
> +		ehci1: usb@11c70100 {
> +			reg =3D <0 0x11c70100 0 0x100>;
> +
> +			/* placeholder */
> +		};
> +
> +		usb2_phy0: usb-phy@11c50200 {
> +			reg =3D <0 0x11c50200 0 0x700>;
> +
> +			/* placeholder */
> +		};
> +
> +		usb2_phy1: usb-phy@11c70200 {
> +			reg =3D <0 0x11c70200 0 0x700>;
> +
> +			/* placeholder */
> +		};
> +
> +		hsusb: usb@11c60000 {
> +			reg =3D <0 0x11c60000 0 0x10000>;
> +
> +			/* placeholder */
> +		};
> +
>  		plic: interrupt-controller@12c00000 {
>  			compatible =3D "renesas,r9a07g043-plic",
> "andestech,nceplic100";
>  			#interrupt-cells =3D <2>;
> @@ -116,5 +248,23 @@ plic: interrupt-controller@12c00000 {
>  			resets =3D <&cpg R9A07G043_NCEPLIC_ARESETN>;
>  			interrupts-extended =3D <&cpu0_intc 11 &cpu0_intc 9>;
>  		};
> +
> +		wdt0: watchdog@12800800 {
> +			reg =3D <0 0x12800800 0 0x400>;
> +
> +			/* placeholder */
> +		};
> +
> +		ostm1: timer@12801400 {
> +			reg =3D <0x0 0x12801400 0x0 0x400>;
> +
> +			/* placeholder */
> +		};
> +
> +		ostm2: timer@12801800 {
> +			reg =3D <0x0 0x12801800 0x0 0x400>;
> +
> +			/* placeholder */
> +		};
>  	};
>  };
> --
> 2.25.1