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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Wed, 21 Sep 2022 10:20:58 +0100
Message-ID: <CA+V-a8t3ukpa1PNz=5fP+BTjWkFJmwDo_EJJYjO9YctF2=K1Vg@mail.gmail.com>
Subject: Re: Similar SoCs with different CPUs and interrupt bindings
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc:     Geert Uytterhoeven <geert@linux-m68k.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Andre Przywara <andre.przywara@arm.com>,
        Conor Dooley <conor.dooley@microchip.com>,
        Samuel Holland <samuel@sholland.org>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Chris Paterson <Chris.Paterson2@renesas.com>,
        Atish Patra <atishp@atishpatra.org>,
        "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>
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Hi Krzysztof,

On Wed, Sep 21, 2022 at 9:53 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 21/09/2022 09:46, Geert Uytterhoeven wrote:
> >         Hi Rob, Krzysztof,
> >
> > This is a topic that came up at the RISC-V BoF at Plumbers, and it was
> > suggested to bring it up with you.
>
> I guess you also need SoC maintainers as well (+Cc Arnd and Olof). :)
>
> >
> > The same SoC may be available with either RISC-V or other (e.g. ARM) CPU
> > cores (an example of this are the Renesas RZ/Five and RZ/G2UL SoCs).
> > To avoid duplication, we would like to have:
> >   - <riscv-soc>.dtsi includes <base-soc>.dtsi,
> >   - <arm-soc>.dtsi includes <base-soc>.dtsi.
> >
> > Unfortunately RISC-V and ARM typically use different types of interrupt
> > controllers, using different bindings (e.g. 2-cell vs. 3-cell), and
> > possibly using different interrupt numbers.  Hence the interrupt-parent
> > and interrupts{-extended} properties should be different, too.
> >
> > Possible solutions[1]:
> >   1. interrupt-map
> >
> >   2. Use a SOC_PERIPHERAL_IRQ() macro in interrupts properties in
> >      <base-soc>.dtsi, with
> >        - #define SOC_PERIPHERAL_IRQ(nr, na) nr          // RISC-V
> >        - #define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI na  // ARM
> >      Note that the cpp/dtc combo does not support arithmetic, so even
> >      the simple case where nr = 32 + na cannot be simplified.
>
> What do you mean? Macros support string concatenation and simple
> arithmetic like adding numbers. I just tested it.
>
I did try the below:

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 689aa4ba416b..0f923c276cd3 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -8,6 +8,8 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/r9a07g043-cpg.h>

+#define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI nr na
+
 / {
     compatible = "renesas,r9a07g043";
     #address-cells = <2>;
@@ -128,7 +130,7 @@ ssi1: ssi@1004a000 {
             compatible = "renesas,r9a07g043-ssi",
                      "renesas,rz-ssi";
             reg = <0 0x1004a000 0 0x400>;
-            interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+            interrupts = <SOC_PERIPHERAL_IRQ(330, IRQ_TYPE_LEVEL_HIGH)>,
                      <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
                      <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
                      <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;

This worked as expected, but couldn't get the arithmetic operation
working. Could you please provide an example?

Cheers,
Prabhakar