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From:   Geert Uytterhoeven <geert@linux-m68k.org>
Date:   Wed, 21 Sep 2022 12:13:17 +0200
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Subject: Re: Similar SoCs with different CPUs and interrupt bindings
To:     Robin Murphy <robin.murphy@arm.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Andre Przywara <andre.przywara@arm.com>,
        Conor Dooley <conor.dooley@microchip.com>,
        Samuel Holland <samuel@sholland.org>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Chris Paterson <Chris.Paterson2@renesas.com>,
        Atish Patra <atishp@atishpatra.org>,
        "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>
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Hi Robin,

On Wed, Sep 21, 2022 at 11:20 AM Robin Murphy <robin.murphy@arm.com> wrote:
> On 2022-09-21 08:46, Geert Uytterhoeven wrote:
> > This is a topic that came up at the RISC-V BoF at Plumbers, and it was
> > suggested to bring it up with you.
> >
> > The same SoC may be available with either RISC-V or other (e.g. ARM) CPU
> > cores (an example of this are the Renesas RZ/Five and RZ/G2UL SoCs).
> > To avoid duplication, we would like to have:
> >    - <riscv-soc>.dtsi includes <base-soc>.dtsi,
> >    - <arm-soc>.dtsi includes <base-soc>.dtsi.
> >
> > Unfortunately RISC-V and ARM typically use different types of interrupt
> > controllers, using different bindings (e.g. 2-cell vs. 3-cell), and
> > possibly using different interrupt numbers.  Hence the interrupt-parent
> > and interrupts{-extended} properties should be different, too.
> >
> > Possible solutions[1]:
> >    1. interrupt-map
> >
> >    2. Use a SOC_PERIPHERAL_IRQ() macro in interrupts properties in
> >       <base-soc>.dtsi, with
> >         - #define SOC_PERIPHERAL_IRQ(nr, na) nr          // RISC-V
> >         - #define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI na  // ARM
> >       Note that the cpp/dtc combo does not support arithmetic, so even
> >       the simple case where nr = 32 + na cannot be simplified.
> >
> >    3. Wrap inside RISCV() and ARM() macros, e.g.:
> >
> >          RISCV(interrupts = <412 IRQ_TYPE_LEVEL_HIGH>;)
> >          ARM(interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;)
> >
> >       Cfr. ARM() and THUMB() in arch/arm/include/asm/unified.h, as used
> >       to express the same operation using plain ARM or ARM Thumb
> >       instructions.
>
> 4. Put all the "interrupts" properties in the SoC-specific DTSI at the
> same level as the interrupt controller to which they correspond. Works
> out of the box with no horrible mystery macros, and is really no more or
> less error-prone than any other approach. Yes, it means replicating a
> bit of structure and/or having labels for everything (many of which may
> be wanted anyway), but that's not necessarily a bad thing for
> readability anyway. Hierarchical definitions are standard FDT practice
> and should be well understood, so this is arguably the simplest and
> least surprising approach :)

Thanks for the suggestion!

It does mean we have to update 3 .dtsi files when adding support
for a new device. As long as all DT changes go through the same (soc)
tree, we can easily manage the dependencies.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds