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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id i1-20020a2e2201000000b0026c0158b87csm549538lji.29.2022.09.21.11.35.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Sep 2022 11:35:38 -0700 (PDT) From: Krzysztof Kozlowski To: robh+dt@kernel.org, Tony Luck , krzysztof.kozlowski+dt@linaro.org, manish.narani@xilinx.com, mchehab@kernel.org, michal.simek@xilinx.com, Sergey.Semin@baikalelectronics.ru, bp@alien8.de Cc: Krzysztof Kozlowski , rric@kernel.org, linux-kernel@vger.kernel.org, krzk@kernel.org, linux-edac@vger.kernel.org, Michail.Ivanov@baikalelectronics.ru, dinguyen@kernel.org, punnaiah.choudary.kalluri@xilinx.com, linux-arm-kernel@lists.infradead.org, Pavel.Parkhomenko@baikalelectronics.ru, robh@kernel.org, james.morse@arm.com, Alexey.Malahov@baikalelectronics.ru, devicetree@vger.kernel.org, fancer.lancer@gmail.com Subject: Re: (subset) [PATCH v2 02/15] dt-bindings: memory: snps: Extend schema with IRQs/resets/clocks props Date: Wed, 21 Sep 2022 20:35:35 +0200 Message-Id: <166378533309.18832.8073645732601460899.b4-ty@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220910195659.11843-3-Sergey.Semin@baikalelectronics.ru> References: <20220910195659.11843-1-Sergey.Semin@baikalelectronics.ru> <20220910195659.11843-3-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 10 Sep 2022 22:56:46 +0300, Serge Semin wrote: > First of all the DW uMCTL2 DDRC IP-core supports the individual IRQ lines > for each standard event: ECC Corrected Error, ECC Uncorrected Error, ECC > Address Protection, Scrubber-Done signal, DFI Parity/CRC Error. It's > possible that the platform engineers merge them up in the IRQ controller > level. So let's add both configuration support to the DT-schema. > > Secondly the DW uMCTL2 DDRC IP-core can have clock sources like APB > reference clock, AXI-ports clock, main DDRC core reference clock and > Scrubber low-power clock. In addition to that each clock domain can have a > dedicated reset signal. Let's add the properties for at least the denoted > clock sources and the corresponding reset controls. > > [...] Applied, thanks! [02/15] dt-bindings: memory: snps: Extend schema with IRQs/resets/clocks props https://git.kernel.org/krzk/linux-mem-ctrl/c/5514acb0dd030356e628cdd88b266efaa0a22315 Best regards, -- Krzysztof Kozlowski