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From:   Rahul Tanwar <rtanwar@maxlinear.com>
To:     <sboyd@kernel.org>, <mturquette@baylibre.com>,
        <linux-clk@vger.kernel.org>
CC:     <linux-kernel@vger.kernel.org>, <linux-lgm-soc@maxlinear.com>,
        "Rahul Tanwar" <rtanwar@maxlinear.com>
Subject: [PATCH RESEND v2 4/5] clk: mxl: Add validation for register reads/writes
Date:   Thu, 22 Sep 2022 14:24:27 +0800
Message-ID: <3bcdfdf0f66dd2fdcffbdeabb5e3ab0bfb2e3489.1663827071.git.rtanwar@maxlinear.com>
In-Reply-To: <cover.1663827071.git.rtanwar@maxlinear.com>
References: <cover.1663827071.git.rtanwar@maxlinear.com>
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Some clocks support parent clock dividers but they do not
support clock gating (clk enable/disable). Such types of
clocks might call API's for get/set_reg_val routines with
width as 0 during clk_prepare_enable() call. Handle such
cases by first validating width during clk_prepare_enable()
while still supporting clk_set_rate() correctly.

Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
---
 drivers/clk/x86/clk-cgu.h | 30 ++++++++++++++++++++++++++----
 1 file changed, 26 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h
index 73ce84345f81..46daf9ebd6c9 100644
--- a/drivers/clk/x86/clk-cgu.h
+++ b/drivers/clk/x86/clk-cgu.h
@@ -299,29 +299,51 @@ struct lgm_clk_branch {
 static inline void lgm_set_clk_val(struct regmap *membase, u32 reg,
 =09=09=09=09   u8 shift, u8 width, u32 set_val)
 {
-=09u32 mask =3D (GENMASK(width - 1, 0) << shift);
+=09u32 mask;
=20
+=09/*
+=09 * Some clocks support parent clock dividers but they do not
+=09 * support clock gating (clk enable/disable). Such types of
+=09 * clocks might call this function with width as 0 during
+=09 * clk_prepare_enable() call. Handle such cases by not doing
+=09 * anything during clk_prepare_enable() but handle clk_set_rate()
+=09 * correctly
+=09 */
+=09if (!width)
+=09=09return;
+
+=09mask =3D (GENMASK(width - 1, 0) << shift);
 =09regmap_update_bits(membase, reg, mask, set_val << shift);
 }
=20
 static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg,
 =09=09=09=09  u8 shift, u8 width)
 {
-=09u32 mask =3D (GENMASK(width - 1, 0) << shift);
+=09u32 mask;
 =09u32 val;
=20
+=09/*
+=09 * Some clocks support parent clock dividers but they do not
+=09 * support clock gating (clk enable/disable). Such types of
+=09 * clocks might call this function with width as 0 during
+=09 * clk_prepare_enable() call. Handle such cases by not doing
+=09 * anything during clk_prepare_enable() but handle clk_set_rate()
+=09 * correctly
+=09 */
+=09if (!width)
+=09=09return 0;
+
 =09if (regmap_read(membase, reg, &val)) {
 =09=09WARN_ONCE(1, "Failed to read clk reg: 0x%x\n", reg);
 =09=09return 0;
 =09}
=20
+=09mask =3D (GENMASK(width - 1, 0) << shift);
 =09val =3D (val & mask) >> shift;
=20
 =09return val;
 }
=20
-
-
 int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
 =09=09=09      const struct lgm_clk_branch *list,
 =09=09=09      unsigned int nr_clk);
--=20
2.17.1