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Sender: Guenter Roeck <groeck7@gmail.com>
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Date:   Thu, 22 Sep 2022 10:43:41 -0700
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Subject: Re: [PATCH v2] watchdog: sp5100_tco: Add "action" module parameter
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To:     rwright@hpe.com, Vladimir Panteleev <git@vladimir.panteleev.md>
Cc:     Wim Van Sebroeck <wim@linux-watchdog.org>,
        linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20220920092721.7686-1-git@vladimir.panteleev.md>
 <20220922173635.GJ18783@rfwz62>
From:   Guenter Roeck <linux@roeck-us.net>
In-Reply-To: <20220922173635.GJ18783@rfwz62>
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On 9/22/22 10:36, rwright@hpe.com wrote:
> On Tue, Sep 20, 2022 at 09:27:21AM +0000, Vladimir Panteleev wrote:
>> Allow configuring the "action" bit, as documented in [1].
>>
>> Previously, the only action supported by this module was to reset the
>> system (0).  It can now be configured to power off (1) instead.
>>
>> [1]: https://www.amd.com/system/files/TechDocs/44413.pdf
> 
> The referenced AMD document 44413 is over 10 years old, and I'm
> concerned when I try to line that document up against the newer versions
> that are implemented in AMD's EPYC processors, that the bit being
> manipulated as SP5100_WDT_ACTION_RESET is effectively reserved in the
> newer references, for example:
> 
>     https://www.amd.com/system/files/TechDocs/55772-A1-PUB.zip
> 
> Is Core::X86::Msr::CpuWdtCfg in the newer document is the same as
> WatchDogControl in the cited 44413.pdf? If so, then I would point out
> that bit 2 is now included in what is called, CpuWdtTimeBase where
> values 2-3H are reserved,  meaning bit 2 effectively must be zero.
> 

I think those may be different watchdogs. Chapter 9.2.6 ("Watchdog
Timer (WDT) Registers") in 55772-A1-PUB still lists bit 2 of the
control register as:

WatchdogAction. Read-write. Reset: 0. 0=System reset. 1=System power off. This bit determines the action to
be taken when the watchdog timer expires. The bit is only valid when the watchdog is enabled.

Guenter