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Date:   Fri, 23 Sep 2022 12:45:26 +0100
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Subject: Re: [PATCH v2 3/3] dmaengine: tegra: Add support for dma-channel-mask
Content-Language: en-US
To:     Akhil R <akhilrajeev@nvidia.com>,
        Laxman Dewangan <ldewangan@nvidia.com>,
        "vkoul@kernel.org" <vkoul@kernel.org>,
        "thierry.reding@gmail.com" <thierry.reding@gmail.com>,
        "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
        "dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
        "linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
References: <20220919112559.58195-1-akhilrajeev@nvidia.com>
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From:   Jon Hunter <jonathanh@nvidia.com>
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On 23/09/2022 12:09, Akhil R wrote:

...

>> Ah OK. I was wondering how this worked with 'channel_reg_size' but
>> looking closer I see channel_reg_size is always SZ_64K. I wonder why we
>> even bother having this parameter and don't use SZ_64K directly?
> There is an offset from the base address which the per channel registers start.
> Although this offset value happens to match with the channel_reg_size, this is
> not actually the per channel register size.

Yes I see that, but I mean why do we even bother having this 
channel_reg_size parameter? Does not look like we need this (currently). 
All we need is ...

  tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET +
                          (i * SZ_64K);

Jon

-- 
nvpublic