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Date:   Fri, 23 Sep 2022 08:46:06 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc:     Ashok Raj <ashok.raj@intel.com>,
        Dave Hansen <dave.hansen@intel.com>,
        Jacob Pan <jacob.jun.pan@intel.com>,
        "Kirill A. Shutemov" <kirill@shutemov.name>,
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        Dave Hansen <dave.hansen@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>,
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        Rick Edgecombe <rick.p.edgecombe@intel.com>,
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Subject: Re: [PATCHv8 00/11] Linear Address Masking enabling
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On Fri, Sep 23, 2022 at 12:38:26PM +0300, Kirill A. Shutemov wrote:

> > So I would assume an untagged pointer should just be fine for the IOMMU
> > to walk. IOMMU currently wants canonical addresses for VA.
> 
> Right. But it means that LAM compatibility can be block on two layers:
> IOMMU and device. IOMMU is not the only HW entity that has to be aware of
> tagged pointers.

Why does a device need to care about this? What do you imagine a
device doing with it?

The userspace should program the device with the tagged address, the
device should present the tagged address on the bus, the IOMMU should
translate the tagged address the same as the CPU by ignoring the upper
bits.

Jason