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Date:   Fri, 23 Sep 2022 13:44:31 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     Dave Hansen <dave.hansen@intel.com>
Cc:     Ashok Raj <ashok.raj@intel.com>,
        "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
        Jacob Pan <jacob.jun.pan@intel.com>,
        "Kirill A. Shutemov" <kirill@shutemov.name>,
        Ashok Raj <ashok_raj@linux.intel.com>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>, x86@kernel.org,
        Kostya Serebryany <kcc@google.com>,
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        "H . J . Lu" <hjl.tools@gmail.com>,
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        Rick Edgecombe <rick.p.edgecombe@intel.com>,
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        Joerg Roedel <joro@8bytes.org>
Subject: Re: [PATCHv8 00/11] Linear Address Masking enabling
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On Fri, Sep 23, 2022 at 09:23:40AM -0700, Dave Hansen wrote:

> After our private chat, I think the answer is that devices *have* a role
> to play.  Device-side logic must know how to untag memory before asking
> for translation or even *deciding* to ask for address translation.  But,
> hopefully, the communicating that untagging information to the device
> will be done in a device-agnostic, standardized way, just how PASIDs or
> ATS are handled today.

Right, that would be my hope, we will see what PCI SIG standardizes.

Jason