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Message-ID: <c9c11931-7193-ebee-51f0-df863dd7377b@linaro.org>
Date:   Fri, 23 Sep 2022 19:52:49 +0200
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Subject: Re: [PATCHv2 3/3] mmc: dw_mmc-pltfm: socfpga: add method to configure
 clk-phase
Content-Language: en-US
To:     Dinh Nguyen <dinguyen@kernel.org>, jh80.chung@samsung.com
Cc:     ulf.hansson@linaro.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, linux-mmc@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
References: <20220922220308.609422-1-dinguyen@kernel.org>
 <20220922220308.609422-4-dinguyen@kernel.org>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <20220922220308.609422-4-dinguyen@kernel.org>
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Precedence: bulk

On 23/09/2022 00:03, Dinh Nguyen wrote:
> The clock-phase settings for the SDMMC controller in the SoCFPGA
> Strarix10/Agilex/N5X platforms reside in a register in the System
> Manager. Add a method to access that register through the syscon
> interface.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> v2: simplify clk-phase calculations
> ---
>  drivers/mmc/host/dw_mmc-pltfm.c | 41 ++++++++++++++++++++++++++++++++-
>  1 file changed, 40 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
> index 9901208be797..5d64984d382f 100644
> --- a/drivers/mmc/host/dw_mmc-pltfm.c
> +++ b/drivers/mmc/host/dw_mmc-pltfm.c
> @@ -17,10 +17,16 @@
>  #include <linux/mmc/host.h>
>  #include <linux/mmc/mmc.h>
>  #include <linux/of.h>
> +#include <linux/mfd/altera-sysmgr.h>
> +#include <linux/regmap.h>
>  
>  #include "dw_mmc.h"
>  #include "dw_mmc-pltfm.h"
>  
> +#define SOCFPGA_DW_MMC_CLK_PHASE_STEP	45
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
> +	((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
> +
>  int dw_mci_pltfm_register(struct platform_device *pdev,
>  			  const struct dw_mci_drv_data *drv_data)
>  {
> @@ -62,9 +68,42 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = {
>  };
>  EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
>  
> +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
> +{
> +	struct device_node *np = host->dev->of_node;
> +	struct regmap *sys_mgr_base_addr;
> +	u32 clk_phase[2] = {0}, reg_offset;
> +	int i, rc, hs_timing;
> +
> +	rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0);
> +	if (rc) {
> +		sys_mgr_base_addr =
> +			altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");

I don't see the reason why this is conditional. Just creates unnecessary
indentation.

> +		if (IS_ERR(sys_mgr_base_addr)) {
> +			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
> +			return 1;
> +		}
> +	} else
> +		return 1;

Why not -ERRNO (or rc)?

> +
> +	of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
> +
> +	for (i = 0; i < ARRAY_SIZE(clk_phase); i++)
> +		clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP;
> +
> +	hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
> +	regmap_write(sys_mgr_base_addr, reg_offset, hs_timing);
> +
> +	return 0;
> +}
> +
> +static const struct dw_mci_drv_data socfpga_drv_data = {
> +	.init		= dw_mci_socfpga_priv_init,
> +};
> +
>  static const struct of_device_id dw_mci_pltfm_match[] = {
>  	{ .compatible = "snps,dw-mshc", },
> -	{ .compatible = "altr,socfpga-dw-mshc", },
> +	{ .compatible = "altr,socfpga-dw-mshc", .data =&socfpga_drv_data, },

Missing space before &

>  	{ .compatible = "img,pistachio-dw-mshc", },
>  	{},
>  };

Best regards,
Krzysztof