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References: <20220919143340.4527-1-vidyas@nvidia.com> <20220919143340.4527-3-vidyas@nvidia.com>
In-Reply-To: <20220919143340.4527-3-vidyas@nvidia.com>
From:   Han Jingoo <jingoohan1@gmail.com>
Date:   Fri, 23 Sep 2022 14:40:35 -0700
Message-ID: <CAPOBaE5yHsQLQssxRX_XF9OYJfWB=F8bTMjchxUswC4F62-Qmw@mail.gmail.com>
Subject: Re: [PATCH V1 2/2] PCI: designware-ep: Disable PTM capabilities for
 EP mode
To:     Vidya Sagar <vidyas@nvidia.com>
Cc:     gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
        robh@kernel.org, kw@linux.com, bhelgaas@google.com,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

On Mon, Sep 19, 2022, Vidya Sagar <vidyas@nvidia.com> wrote:
>
> Dual mode DesignWare PCIe IP has PTM capability enabled (if supported) even
> in the EP mode. The PCIe compliance for the EP mode expects PTM
> capabilities (ROOT_CAPABLE, RES_CAPABLE, CLK_GRAN) be disabled.
> Hence disable PTM for the EP mode.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
>  .../pci/controller/dwc/pcie-designware-ep.c   | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 7e9529ae3824..dc3057b18f36 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -646,7 +646,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>         struct dw_pcie_ep_func *ep_func;
>         struct device *dev = pci->dev;
>         struct pci_epc *epc = ep->epc;
> -       unsigned int offset;
> +       unsigned int offset, ptm_cap_base;

Is there any reason to mix these 2 variables into 1 line?
If not, please add a new line for ptm_cap_base.

       unsigned int offset;
       unsigned int ptm_cap_base;

Also, it looks ok. When you send a new patch, just add my Acked-by.
Acked-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han

>         unsigned int nbars;
>         u8 hdr_type;
>         u8 func_no;
> @@ -698,6 +698,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>         }
>
>         offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
> +       ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
>
>         dw_pcie_dbi_ro_wr_en(pci);
>
> @@ -710,6 +711,22 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>                         dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
>         }
>
> +       /*
> +        * PTM responder capability can be disabled only after disabling
> +        * PTM root capability.
> +        */
> +       if (ptm_cap_base) {
> +               dw_pcie_dbi_ro_wr_en(pci);
> +               reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
> +               reg &= ~PCI_PTM_CAP_ROOT;
> +               dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
> +
> +               reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
> +               reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK);
> +               dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
> +               dw_pcie_dbi_ro_wr_dis(pci);
> +       }
> +
>         dw_pcie_setup(pci);
>         dw_pcie_dbi_ro_wr_dis(pci);
>
> --
> 2.17.1
>