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References: <20220919143340.4527-1-vidyas@nvidia.com> <20220919143340.4527-2-vidyas@nvidia.com>
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From:   Han Jingoo <jingoohan1@gmail.com>
Date:   Fri, 23 Sep 2022 14:37:07 -0700
Message-ID: <CAPOBaE63bAnzEzz+xkSN-J1sGxBgv4-tnJO-AjxsxPDzZcaViA@mail.gmail.com>
Subject: Re: [PATCH V1 1/2] PCI: Add PCI_PTM_CAP_RES macro
To:     Vidya Sagar <vidyas@nvidia.com>
Cc:     gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
        robh@kernel.org, kw@linux.com, bhelgaas@google.com,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com
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On Mon, Sep 19, 2022 Vidya Sagar <vidyas@nvidia.com> wrote:
>
> Add macro defining Responder capable bit in Precision Time Measurement
> capability register.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>

Reviewed-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han

> ---
>  include/uapi/linux/pci_regs.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 57b8e2ffb1dd..1c3591c8e09e 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -1058,6 +1058,7 @@
>  /* Precision Time Measurement */
>  #define PCI_PTM_CAP                    0x04        /* PTM Capability */
>  #define  PCI_PTM_CAP_REQ               0x00000001  /* Requester capable */
> +#define  PCI_PTM_CAP_RES               0x00000002  /* Responder capable */
>  #define  PCI_PTM_CAP_ROOT              0x00000004  /* Root capable */
>  #define  PCI_PTM_GRANULARITY_MASK      0x0000FF00  /* Clock granularity */
>  #define PCI_PTM_CTRL                   0x08        /* PTM Control */
> --
> 2.17.1
>